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1. 发明授权

US5939790A Integrated circuit pad structures 失效
标题翻译：集成电路板结构
公开(公告)号：US5939790A
公开(公告)日：1999-08-17
申请号：US631667
申请日：1996-04-09
申请人： Francois Gregoire , Raminda Madurawe , Guru Thalapaneni
发明人： Francois Gregoire , Raminda Madurawe , Guru Thalapaneni
IPC分类号： H01L23/485 , H01L23/48 , H01L21/60
CPC分类号： H01L24/05 , H01L2224/05093 , H01L2224/05095 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/05042 , H01L2924/14
摘要： Pad structures for an integrated circuit are provided that use via holes or slots rather than large pad openings to form electrical connections between successive metal interconnection layers. The via holes or slots are filled using standard metal etchback deposition techniques. The pad structures minimize particle generation during circuit fabrication. A number of the via holes or slots in the pad structure can be interconnected in parallel to provide a sufficient current handling capacity to distribute power to the active components on the integrated circuit.
摘要翻译：提供了用于集成电路的焊盘结构，其使用通孔或狭槽而不是大的焊盘开口以在连续的金属互连层之间形成电连接。使用标准金属回蚀沉积技术填充通孔或槽。焊盘结构使电路制造过程中的颗粒产生最小化。焊盘结构中的多个通孔或槽可以并联连接以提供足够的电流处理能力以将功率分配给集成电路上的有源部件。

2. 发明授权

US07573293B2 Programmable logic based latches and shift registers 有权
标题翻译：可编程逻辑锁存器和移位寄存器
公开(公告)号：US07573293B2
公开(公告)日：2009-08-11
申请号：US12119490
申请日：2008-05-12
申请人： Raminda Madurawe , Nij Dorairaj
发明人： Raminda Madurawe , Nij Dorairaj
IPC分类号： H03K19/173
CPC分类号： H03K19/1736
摘要： A latch is described, comprising: a first programmable logic element (LE); and a second programmable logic element (LE); and an output of the first LE adapted to directly couple to a first input of the second LE; and an output of the second LE coupled to a first input of the first LE; and a first common input coupled to a second input of the first and second LE; and a second common input coupled to a third input of the first and second LE.
摘要翻译：描述了锁存器，包括：第一可编程逻辑元件（LE）; 和第二可编程逻辑元件（LE）; 以及适于直接耦合到第二LE的第一输入端的第一LE的输出; 以及耦合到第一LE的第一输入端的第二LE的输出; 以及耦合到所述第一和第二LE的第二输入的第一公共输入; 以及耦合到第一和第二LE的第三输入的第二公共输入。

3. 发明申请

US20090129174A1 MULTI-PORT THIN-FILM MEMORY DEVICES 有权
标题翻译：多端口薄膜存储器件
公开(公告)号：US20090129174A1
公开(公告)日：2009-05-21
申请号：US12172989
申请日：2008-07-14
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/16 , G11C11/412
摘要： In a first aspect, a semiconductor storage device, comprising: a metal line coupled to a gate of an access transistor, wherein the gate material is deposited substantially above the metal line. In a second aspect, a semiconductor storage device, comprising: a first port to write data to a storage element; and a second port to read a signal generated by the storage element; and a first metal line coupled to a gate of an access transistor coupled to the first port; and a second metal line coupled to a gate of an access transistor coupled to the second port; wherein, the gates of said access transistors are formed on a gate material deposited substantially above the metal of first and second metal lines.
摘要翻译：在第一方面，一种半导体存储装置，包括：耦合到存取晶体管的栅极的金属线，其中栅极材料基本上沉积在金属线的上方。在第二方面中，一种半导体存储装置，包括：向存储元件写入数据的第一端口; 以及第二端口，用于读取由所述存储元件生成的信号; 以及耦合到耦合到所述第一端口的存取晶体管的栅极的第一金属线; 以及耦合到耦合到所述第二端口的存取晶体管的栅极的第二金属线; 其中，所述存取晶体管的栅极形成在基本上沉积在第一和第二金属线的金属上方的栅极材料上。

4. 发明申请

US20070171105A1 Look-up table structure with embedded carry logic 有权
标题翻译：具有嵌入式进位逻辑的查找表结构
公开(公告)号：US20070171105A1
公开(公告)日：2007-07-26
申请号：US11728839
申请日：2007-03-28
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03M7/00
CPC分类号： H03K19/1737 , H03K19/177
摘要： A programmable look-up-table (LUT) structure adapted for carry logic incrementer implementation in an integrated circuit, comprising: three or more data inputs and a carry-in input, said data inputs comprised of consecutive bits in a data string, said carry-in comprised of the increment value to the least order bit of said data string; and three or more data outputs and a carry-out output, said data outputs comprised of the incremented values of said data inputs, and said carry-out resulting from the incremented value of the highest order bit of said data inputs; wherein, said three or more data outputs are computed in a single carry computation stage within the LUT structure.
摘要翻译：一种适于在集成电路中进行进位逻辑增量器实现的可编程查找表（LUT）结构，包括：三个或更多个数据输入和进位输入，所述数据输入由数据串中的连续位组成，所述进位 -in包括对所述数据串的最小位的增量值; 以及三个或更多个数据输出和进位输出，所述数据输出包括所述数据输入的递增值，以及由所述数据输入的最高位的递增值产生的所述进位输出; 其中，在LUT结构内的单个进位计算阶段中计算所述三个或更多个数据输出。

5. 发明申请

US20060152248A1 Configuration circuits for programmable logic devices 有权
标题翻译：可编程逻辑器件的配置电路
公开(公告)号：US20060152248A1
公开(公告)日：2006-07-13
申请号：US11365031
申请日：2006-03-02
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/177
CPC分类号： H03K19/17724 , H01L21/8221 , H01L27/0688 , H03K19/1735 , H03K19/177 , H03K19/17736 , H03K19/17748 , H03K19/17796
摘要： Configuration circuits wherein configurable elements comprise low conducting on currents and/or low on to off current ratios for programmable logic devices are disclosed. A semiconductor device, wherein: a programmable logic circuit is configured by a control signal received at a capacitive node in the circuit, wherein the control signal is further generated by one of: a low conducting current pull-up configurable element configured to couple the control signal to a power supply voltage; and a low conducting current pull-down configurable element configured to couple the control signal to a ground supply voltage; wherein, the low conducting current charge the capacitive node to either the power or ground voltage levels.
摘要翻译：公开了其中可配置元件包括用于可编程逻辑器件的低导通导通电流和/或低导通到截止电流比的配置电路。一种半导体器件，其中：可编程逻辑电路由在所述电路中的电容性节点处接收的控制信号配置，其中所述控制信号由以下之一产生：低导通电流上拉可配置元件，其被配置为将所述控制信号信号到电源电压; 以及低导通电流下拉可配置元件，其被配置为将所述控制信号耦合到接地电源电压; 其中，低导通电流将电容性节点充电到电源或接地电压电平。

6. 发明申请

US20050007839A1 Semiconductor switching devices 有权
标题翻译：半导体开关器件
公开(公告)号：US20050007839A1
公开(公告)日：2005-01-13
申请号：US10912697
申请日：2004-08-06
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： G11C5/00 , G11C11/00 , H01L21/822 , H01L21/84 , H01L27/01 , H01L27/06 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/0688 , H01L21/8221 , H01L21/84 , H01L27/12
摘要： A compact switching device for applications in integrated circuits is disclosed. The switching device comprises a P-type conductive channel and an N-type conductive channel, both formed on a very-thin semiconductor film. A lightly doped portion in each of said conductive channels is controlled by a single gate electrode formed on a dielectric layer above the channel regions. These lightly doped portions are designed to provide an enhanced conductive state by accumulating majority carriers at the surface, and a non-conductive state by fully depleting majority carriers from the entire thin-film thickness from the single gate electrode provided. Both gate electrodes are coupled to a common input, and both drain nodes are coupled to a common output. Design parameters are optimized to provide complementary devices side-by-side on a single geometry of the thin film, merged at the common drain node.
摘要翻译：公开了一种用于集成电路中的紧凑型开关装置。开关器件包括形成在非常薄的半导体膜上的P型导电沟道和N型导电沟道。每个所述导电通道中的轻掺杂部分由形成在沟道区上方的电介质层上的单个栅电极控制。这些轻掺杂部分被设计成通过在表面累积多数载流子来提供增强的导电状态，并且通过从提供的单个栅电极全部耗尽整个薄膜厚度的多数载流子来提供增强的导电状态。两个栅电极耦合到公共输入，并且两个漏极节点耦合到公共输出。优化设计参数以在薄膜的单个几何结构上并排提供互补器件，并在公共漏极节点处合并。

7. 发明授权

US5696455A Reconfigurable programmable logic device 失效
标题翻译：可重构可编程逻辑器件
公开(公告)号：US5696455A
公开(公告)日：1997-12-09
申请号：US697103
申请日：1996-08-19
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/177
CPC分类号： H03K19/17756 , H03K19/17704
摘要： The present invention provides a reconfigurable programmable logic device (PLD) that saves its own programmed state without the use of an external memory device or without additional control logic on the PLD. A non-volatile memory cell is incorporated with each SRAM cell in the PLD to form a configuration memory cell. The non-volatile memory cells store the programmed states of the associated SRAM cells even after termination of power to the system. Each non-volatile memory cell then restores the configured state of its associated SRAM cell upon system power-up by "mapping" its contents to the SRAM cell. The non-volatile memory cell may be implemented either by an Erasable Programmable Read Only Memory cell ("EPROM") or an Electrically Erasable Programmable Read Only Memory cell ("EEPROM").
摘要翻译：本发明提供了可重新配置的可编程逻辑器件（PLD），其在不使用外部存储器件的情况下保存其自己的编程状态，或者在PLD上没有附加的控制逻辑。非易失性存储单元与PLD中的每个SRAM单元并入，以形成配置存储单元。非易失性存储器单元即使在终止电力系统之后也存储相关SRAM单元的编程状态。然后，通过将其内容“映射”到SRAM单元，系统上电时，每个非易失性存储单元恢复其关联的SRAM单元的配置状态。非易失性存储单元可以由可擦除可编程只读存储单元（“EPROM”）或电可擦除可编程只读存储单元（“EEPROM”）来实现。

8. 发明授权

US5138576A Method and apparatus for erasing an array of electrically erasable EPROM cells 失效
标题翻译：擦除电可擦除EPROM单元阵列的方法和装置
公开(公告)号：US5138576A
公开(公告)日：1992-08-11
申请号：US788606
申请日：1991-11-06
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/14 , G11C16/16
CPC分类号： G11C16/3477 , G11C16/14 , G11C16/16
摘要： A method and apparatus for erasing an array of electrically erasable EPROM cells that avoids overerasure and allows programming or erasure of individual cells are provided. An erase line for each column of the array applies erase potential to the erase node of each cell in the column, provided that the erase node is connected to the erase line by a transistor controlled by a row select line. A sense amplifier determines when each cell begins to conduct and disconnects that cell from its erase line. By selecting a particular row, and then applying erase potential only to selected erase lines, a pattern of erased and programmed cells can be created in each row. The pattern differs from row to row depending on which erase lines have erase potential applied when that row is selected. Bias differences between erase and read modes assure that the erased cells, which have gone slightly into depletion, are not in depletion in normal operation.

9. 发明授权

US07656190B2 Incrementer based on carry chain compression 有权
标题翻译：基于进位链压缩的增量器
公开(公告)号：US07656190B2
公开(公告)日：2010-02-02
申请号：US12480213
申请日：2009-06-08
申请人： Nij Dorairaj , Raminda Madurawe
发明人： Nij Dorairaj , Raminda Madurawe
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , G11C7/1006 , G11C11/419 , G11C2207/102
摘要： A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive-OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output.
摘要翻译：公开了一种用于递增或减少n位数据的计算单元。该单元具有用于处理n位数据的n / 3个逻辑块，每个逻辑块包括：第一和第二多路复用器，用于传播进位链; 以及耦合到多路复用器的进位链的第一，第二和第三异或（XOR）电路，以产生3位递增的输出。

10. 发明申请

US20080068041A1 Look-up table structure with embedded carry logic 有权
标题翻译：具有嵌入式进位逻辑的查找表结构
公开(公告)号：US20080068041A1
公开(公告)日：2008-03-20
申请号：US11985830
申请日：2007-11-19
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , H01H9/40 , H01H9/563 , Y10T307/937
摘要： A configurable look up table (LUT) structure of an integrated circuit comprising: a first, a second and a third intermediate LUT stage, each of the LUT stages comprising one or more inputs and an output, wherein: the output of first intermediate LUT stage is coupled to an input of the second and third intermediate LUT stages; and the second intermediate LUT stage generates an arithmetic function of two bits and a carry-in signal received as inputs to the LUT structure; and the third intermediate LUT stage generates a carry-out signal.
摘要翻译：一种集成电路的可配置查找表（LUT）结构，包括：第一，第二和第三中间LUT级，每个LUT级包括一个或多个输入和输出，其中：第一中间LUT级的输出耦合到第二和第三中间LUT级的输入; 并且第二中间LUT阶段产生两个比特的算术函数和作为LUT结构的输入接收的进位信号; 并且第三中间LUT级产生进位信号。

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