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1. 发明申请

US20060292783A1 CMOS transistor and method of manufacturing the same 有权
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US20060292783A1
公开(公告)日：2006-12-28
申请号：US11363176
申请日：2006-02-28
申请人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
发明人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
IPC分类号： H01L21/8238 , H01L29/80
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.
摘要翻译：公开了一种CMOS晶体管结构及相关的制造方法，其中第一导电型MOS晶体管包括增强器，第二导电类型MOS晶体管包括由与增强器相同的材料形成的第二间隔物。第二导电型MOS晶体管还包括相对于形成在凹陷区域中的外延层形成的源极/漏极区域。

2. 发明授权

US07315063B2 CMOS transistor and method of manufacturing the same 有权
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US07315063B2
公开(公告)日：2008-01-01
申请号：US11363176
申请日：2006-02-28
申请人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
发明人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.
摘要翻译：公开了一种CMOS晶体管结构及相关的制造方法，其中第一导电型MOS晶体管包括增强器，第二导电类型MOS晶体管包括由与增强器相同的材料形成的第二间隔物。第二导电型MOS晶体管还包括相对于形成在凹陷区域中的外延层形成的源极/漏极区域。

3. 发明授权

US08273620B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US08273620B2
公开(公告)日：2012-09-25
申请号：US12793809
申请日：2010-06-04
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

4. 发明授权

US07755133B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US07755133B2
公开(公告)日：2010-07-13
申请号：US11855529
申请日：2007-09-14
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

5. 发明申请

US20100068868A1 Wafer temporary bonding method using silicon direct bonding 有权
标题翻译：晶圆临时接合方法采用硅直接接合
公开(公告)号：US20100068868A1
公开(公告)日：2010-03-18
申请号：US12585537
申请日：2009-09-17
申请人： Jung-ho Kim , Dae-lok Bae , Jong-wook Lee , Seung-woo Choi , Pil-kyu Kang
发明人： Jung-ho Kim , Dae-lok Bae , Jong-wook Lee , Seung-woo Choi , Pil-kyu Kang
IPC分类号： H01L21/762
CPC分类号： H01L21/6835 , H01L24/83 , H01L24/94 , H01L25/50 , H01L2221/6835 , H01L2221/68359 , H01L2224/83 , H01L2924/01005 , H01L2924/01006 , H01L2924/01021 , H01L2924/01033 , H01L2924/01047 , H01L2924/10253 , H01L2924/00
摘要： A wafer temporary bonding method using silicon direct bonding (SDB) may include preparing a carrier wafer and a device wafer, adjusting roughness of a surface of the carrier wafer, and combining the carrier wafer and the device wafer using the SDB. Because the method uses SDB, instead of an adhesive layer, for a temporary bonding process, a module or process to generate and remove an adhesive is unnecessary. Also, a defect in a subsequent process, for example, a back-grinding process, due to irregularity of the adhesive may be prevented.
摘要翻译：使用硅直接接合（SDB）的晶片临时接合方法可以包括制备载体晶片和器件晶片，调整载体晶片的表面的粗糙度，以及使用SDB组合载体晶片和器件晶片。因为该方法使用SDB而不是粘合剂层用于临时粘接过程，所以不需要用于产生和去除粘合剂的模块或工艺。此外，可以防止由于粘合剂的不规则性而导致的后续工艺中的缺陷，例如后磨削工艺。

6. 发明授权

US06935225B2 Bread maker 失效
标题翻译：面包机
公开(公告)号：US06935225B2
公开(公告)日：2005-08-30
申请号：US10602643
申请日：2003-06-25
申请人： Jae-ryong Park , Jong-wook Lee , Tae-uk Lee , Han-jun Sung
发明人： Jae-ryong Park , Jong-wook Lee , Tae-uk Lee , Han-jun Sung
IPC分类号： A47J37/00 , A21B1/00 , A21B7/00 , A47J43/04 , A23L1/00 , A21C1/08 , A47J27/62 , A47J37/01
CPC分类号： A21B7/005
摘要： A bread maker, including a main body having a baking space and kneading drums located at an upper part and a lower part in the baking space. The kneading drums hold opposite ends of a mixing bag. A movable tray member has a plurality of combining projections at opposite side walls thereof. A fixed tray member positioned opposite the movable tray member forms a slit through which the mixing bag passes. A tray holder is coupled to each end of the fixed tray member and the movable tray member. Each tray holder fixedly supports the fixed tray member, and has a plurality of guide grooves accommodating the combining projections to rotatably support the movable tray member. Anchoring prominences are on the guide grooves adjacent to the fixed tray member, preventing the combining projections from breaking away from the guide grooves when the movable tray member rotates.
摘要翻译：面包机，包括具有烘烤空间的主体和位于烘焙空间中的上部和下部的捏合桶。捏捏桶保持混合袋的两端。可移动托盘构件在其相对侧壁处具有多个组合突起。与可移动托盘构件相对定位的固定托盘构件形成混合袋通过的狭缝。托盘保持器联接到固定托盘构件和可移动托盘构件的每个端部。每个托盘支架固定地支撑固定托盘构件，并且具有容纳组合突起的多个引导槽，以可旋转地支撑可动托盘构件。锚定凸起位于与固定托盘构件相邻的引导槽上，防止组合突起在可动托盘构件旋转时从引导槽脱离。

7. 发明申请

US20120097950A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：US20120097950A1
公开(公告)日：2012-04-26
申请号：US13343967
申请日：2012-01-05
申请人： Yong-hoon SON , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon SON , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/786 , H01L21/28
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

8. 发明授权

US06933569B2 SOI MOSFET 失效
公开(公告)号：US06933569B2
公开(公告)日：2005-08-23
申请号：US10668349
申请日：2003-09-24
申请人： Risho Koh , Shigeharu Yamagami , Jong-wook Lee , Hitoshi Wakabayashi , Yukishige Saito , Atsushi Ogura , Mitsuru Narihiro , Kohichi Arai , Hisashi Takemura , Tohru Mogami , Toyoji Yamamoto , Yukinori Ochiai
发明人： Risho Koh , Shigeharu Yamagami , Jong-wook Lee , Hitoshi Wakabayashi , Yukishige Saito , Atsushi Ogura , Mitsuru Narihiro , Kohichi Arai , Hisashi Takemura , Tohru Mogami , Toyoji Yamamoto , Yukinori Ochiai
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L21/01
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/78609 , H01L29/78615 , H01L29/78621
摘要： A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.
摘要翻译：半导体器件包括形成在绝缘体上的半导体层，形成在半导体层上的栅极绝缘膜，形成在栅极绝缘膜上并沿第一方向延伸的栅电极，在两侧的半导体层中形成的源/漏区所述半导体层中的主体接触区域，其中比所述栅极绝缘膜更厚的场绝缘膜介于所述半导体层和所述栅电极的延伸部分之间的部分隔离区域，以及完全隔离区域去除绝缘体上的半导体层。完全隔离区域形成为与平行于源极/漏极区域的第一方向的一侧的至少一部分接触。

9. 发明授权

US06779439B2 Bread maker 失效
标题翻译：面包机
公开(公告)号：US06779439B2
公开(公告)日：2004-08-24
申请号：US10459536
申请日：2003-06-12
申请人： Jong-wook Lee , Tae-uk Lee , Han-jun Sung , Jae-ryong Park
发明人： Jong-wook Lee , Tae-uk Lee , Han-jun Sung , Jae-ryong Park
IPC分类号： A23L100
CPC分类号： A21B7/005
摘要： A bread maker having a main body forming an oven compartment, a door, a pair of parallel kneading drums, a barcode reader to read a barcode printed on a mixing bag and a reader holder. The reader holder includes a holder body, a sensing lever adjacent to a kneading drum with one end connected to one end of the holder body and the other end protruding from the main body towards the door, the sensing lever being pushed back by the door when the door is closed, and a reader supporting part extending from the holder body towards the door and supporting the barcode reader. The barcode reader moves into a reading position near the adjacent kneading drum when the door is opened and moves into a releasing position distant from the adjacent kneading drum when the door is closed.
摘要翻译：一种面包机，其主体形成烤箱室，门，一对平行的捏合桶，条形码读取器，用于读取打印在混合袋上的条形码和读取器保持器。读取器保持器包括保持器主体，与捏合滚筒相邻的感测杆，一端连接到保持器主体的一端，另一端从主体朝向门突出，感测杆被门推回，门被关闭，读取器支撑部分从保持器本体朝向门延伸并支撑条形码读取器。当门打开时，条形码读取器移动到相邻捏合鼓附近的读取位置，并且当门关闭时移动到远离相邻捏合鼓的释放位置。

10. 发明授权

US06645674B2 Ether derivative additive in nonaqueous electrolyte of a lithium secondary battery 有权
标题翻译：锂二次电池非水电解液中的醚衍生物添加剂
公开(公告)号：US06645674B2
公开(公告)日：2003-11-11
申请号：US09761764
申请日：2001-01-18
申请人： Jeong-soon Shin , Jin-sung Kim , Eui-sun Hong , Jong-wook Lee , Young-gyu Kim , Jong-seob Kim
发明人： Jeong-soon Shin , Jin-sung Kim , Eui-sun Hong , Jong-wook Lee , Young-gyu Kim , Jong-seob Kim
IPC分类号： H01M458
CPC分类号： H01M10/052 , H01M10/0567 , H01M10/4235
摘要： The present invention provides a lithium secondary battery comprising a cathode electrode containing a lithium complex oxide; an anode electrode containing metal lithium or its alloy, or carbon material; and a nonaqueous organic electrolyte containing a nonaqueous organic solvent, a lithium salt and an aromatic ether that can react to form dimers or polymers above a certain temperature and voltage and that can be expressed by Formula 1 below: wherein, R1 is independently a single bond or an alkylene group with less than or equal to 2 carbons and R2 is hydrogen or an alkyl group with less than or equal to 2 carbons. The lithium secondary battery has the advantage that its characteristics are maintained, even if it is left in its fully charged state at a high temperature for a long time and, at the same time, its reliability and stability have been improved.
摘要翻译：本发明提供一种锂二次电池，其包含含有锂复合氧化物的阴极电极; 含有金属锂或其合金或碳材料的阳极电极; 以及含有非水有机溶剂，锂盐和芳族醚的非水有机电解质，其能够反应以形成高于一定温度和电压的二聚体或聚合物，并且可以由下式1表示：其中，R 1独立地为单键或具有小于或等于2个碳的亚烷基，R 2是氢或具有小于或等于2个碳的烷基。锂二次电池具有保持其特性的优点，即使其完全保留在高温下充电状态长时间，同时其可靠性和稳定性得到提高。

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