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1. 发明授权

US07940126B2 Signal amplification apparatus with advanced linearization 有权
标题翻译：具有高级线性化的信号放大装置
公开(公告)号：US07940126B2
公开(公告)日：2011-05-10
申请号：US12625201
申请日：2009-11-24
申请人： Young-Wan Choi , Do-Gyun Kim , Nam-Pyo Hong
发明人： Young-Wan Choi , Do-Gyun Kim , Nam-Pyo Hong
IPC分类号： H03F3/04
CPC分类号： H03F1/223 , H03F1/3205 , H03F2200/108 , H03F2200/181 , H03F2200/451
摘要： Provided is a signal amplification apparatus with advanced linearization, the signal amplification apparatus including: a driving unit having a structure of a cascode amplifier including a first active element and a second active element and outputting an amplification signal in which an input signal is amplified, to an output terminal; a third active element receiving a signal diverged between the first active element and the second active element while gate and drain terminals of the third active element are shorted; a fourth active element of which gate and drain terminals are connected to a source terminal of the third active element; and a fifth active element of which gate terminal is connected to the drain terminal of the fourth active element, outputting a non-linear signal having an opposite phase to the amplification signal to the output terminal so as to cancel a third-order inter-modulation distortion component included in the input signal. An amplification signal in which an input signal is amplified is combined with a non-linear signal having an opposite phase to the amplification signal and a low gain and is output so that a third-order inter-modulation distortion component included in the input signal can be cancelled and a signal with advanced linearity can be output.
摘要翻译：提供一种具有高级线性化的信号放大装置，该信号放大装置包括：驱动单元，具有包括第一有源元件和第二有源元件的共源共栅放大器的结构，并输出其中输入信号被放大的放大信号，输出端子; 第三有源元件接收在第一有源元件和第二有源元件之间发散的信号，同时第三有源元件的栅极和漏极端子短路; 栅极和漏极端子连接到第三有源元件的源极端子的第四有源元件; 以及第五有源元件，其栅极端子连接到第四有源元件的漏极端子，向输出端子输出具有与放大信号相反的相位的非线性信号，以消除三阶互调失真分量包含在输入信号中。其中输入信号被放大的放大信号与与放大信号具有相反相位的非线性信号和低增益组合，并被输出，使得输入信号中包括的三阶互调失真分量可以被取消，并且可以输出具有高线性度的信号。

2. 发明授权

US07768333B2 Apparatus and method of generating reference clock for DLL circuit 有权
标题翻译：生成DLL电路参考时钟的装置和方法
公开(公告)号：US07768333B2
公开(公告)日：2010-08-03
申请号：US11819260
申请日：2007-06-26
申请人： Nam-Pyo Hong
发明人： Nam-Pyo Hong
IPC分类号： H03K3/00
CPC分类号： H03K5/1565
摘要： An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.
摘要翻译：一种用于产生DLL电路的参考时钟的装置包括：缓冲单元，被配置为缓冲外部时钟，以产生第一参考时钟和第二参考时钟，并且反转第二参考时钟，以产生负的第二参考时钟。占空比补偿单元从第一参考时钟和负第二参考时钟产生参考时钟。

3. 发明授权

US08049544B2 Delay locked loop circuit 失效
标题翻译：延时锁定回路电路
公开(公告)号：US08049544B2
公开(公告)日：2011-11-01
申请号：US12627179
申请日：2009-11-30
申请人： Nam-Pyo Hong , Jin-Youp Cha
发明人： Nam-Pyo Hong , Jin-Youp Cha
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , G11C7/222 , H03L7/0814
摘要： A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock.
摘要翻译：延迟锁定环电路包括：相位比较单元，被配置为将参考时钟与反馈时钟进行比较并输出相位比较信号;时钟延迟单元，被配置为响应于相位比较信号延迟第一参考时钟，以输出第一延迟锁定时钟，根据频率信息信号延迟第一延迟锁定时钟和第二参考时钟之一，并输出第二延迟锁定时钟;延迟锁定时钟生成单元，被配置为输出延迟锁定时钟作为第一延迟锁定时钟和第二延迟锁定时钟的相位混合时钟，第一延迟锁定时钟或响应于频率信息信号和延迟传递信号的第二延迟锁定时钟，以及延迟复制模型单元，被配置为反映参考时钟的延迟状况。

4. 发明授权

US07902899B2 Apparatus and method of generating reference clock for DLL circuit 有权
标题翻译：生成DLL电路参考时钟的装置和方法
公开(公告)号：US07902899B2
公开(公告)日：2011-03-08
申请号：US12820545
申请日：2010-06-22
申请人： Nam-Pyo Hong
发明人： Nam-Pyo Hong
IPC分类号： H03K3/00
CPC分类号： H03K5/1565
摘要： An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock.
摘要翻译：一种用于产生DLL电路的参考时钟的装置包括：缓冲单元，被配置为缓冲外部时钟，以产生第一参考时钟和第二参考时钟，并且反转第二参考时钟，以产生负的第二参考时钟。占空比补偿单元从第一参考时钟和负第二参考时钟产生参考时钟。

5. 发明申请

US20110001526A1 DELAY LOCKED LOOP CIRCUIT 失效
标题翻译：延迟锁定环路
公开(公告)号：US20110001526A1
公开(公告)日：2011-01-06
申请号：US12627179
申请日：2009-11-30
申请人： Nam-Pyo Hong , Jin-Youp Cha
发明人： Nam-Pyo Hong , Jin-Youp Cha
IPC分类号： H03L7/08
CPC分类号： H03L7/0816 , G11C7/222 , H03L7/0814
摘要： A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock.
摘要翻译：延迟锁定环电路包括：相位比较单元，被配置为将参考时钟与反馈时钟进行比较并输出相位比较信号;时钟延迟单元，被配置为响应于相位比较信号延迟第一参考时钟，以输出第一延迟锁定时钟，根据频率信息信号延迟第一延迟锁定时钟和第二参考时钟之一，并输出第二延迟锁定时钟;延迟锁定时钟生成单元，被配置为输出延迟锁定时钟作为第一延迟锁定时钟和第二延迟锁定时钟的相位混合时钟，第一延迟锁定时钟或响应于频率信息信号和延迟传递信号的第二延迟锁定时钟，以及延迟复制模型单元，被配置为反映参考时钟的延迟状况。

6. 发明申请

US20100295589A1 MULTI-STAGE DIFFERENTIAL AMPLIFICATION CIRCUIT AND INPUT BUFFER FOR SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于半导体器件的多级差分放大电路和输入缓冲器
公开(公告)号：US20100295589A1
公开(公告)日：2010-11-25
申请号：US12494485
申请日：2009-06-30
申请人： Nam-Pyo Hong
发明人： Nam-Pyo Hong
IPC分类号： H03L7/06 , H03F3/45
CPC分类号： H03K5/249
摘要： A multi-stage amplification circuit includes a common differential amplification unit configured to receive and detect differential input signals to generate a positive signal and a negative signal, a positive signal amplification unit configured to receive the positive signal and the negative signal through differential input terminals to generate a positive amplification signal, and a negative signal amplification unit configured to receive the positive signal and the negative signal through differential input terminals to generate a negative amplification signal.
摘要翻译：多级放大电路包括：公共差分放大单元，被配置为接收和检测差分输入信号以产生正信号和负信号;正信号放大单元，被配置为通过差分输入端接收正信号和负信号，产生正放大信号，负信号放大单元被配置为通过差分输入端接收正信号和负信号以产生负放大信号。

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