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1. 发明申请

US20140361403A1 SEMICONDUCTOR DEVICES INCLUDING CAPACITORS 有权
标题翻译：包括电容器的半导体器件
公开(公告)号：US20140361403A1
公开(公告)日：2014-12-11
申请号：US14296850
申请日：2014-06-05
申请人： Young-Seung Cho , Sung-Eui Kim , Ji-Young Kim , Hoon Jeong , Chan-Won Kim , Jong-Bom Seo , Seung-Jun Lee , Jun-Soo Lee
发明人： Young-Seung Cho , Sung-Eui Kim , Ji-Young Kim , Hoon Jeong , Chan-Won Kim , Jong-Bom Seo , Seung-Jun Lee , Jun-Soo Lee
IPC分类号： H01L49/02
CPC分类号： H01L28/88 , H01L21/764 , H01L27/10808 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/90
摘要： A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
摘要翻译：半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

2. 发明授权

US09330960B2 Semiconductor devices including capacitors 有权
标题翻译：半导体器件包括电容器
公开(公告)号：US09330960B2
公开(公告)日：2016-05-03
申请号：US14296850
申请日：2014-06-05
申请人： Young-Seung Cho , Sung-Eui Kim , Ji-Young Kim , Hoon Jeong , Chan-Won Kim , Jong-Bom Seo , Seung-Jun Lee , Jun-Soo Lee
发明人： Young-Seung Cho , Sung-Eui Kim , Ji-Young Kim , Hoon Jeong , Chan-Won Kim , Jong-Bom Seo , Seung-Jun Lee , Jun-Soo Lee
IPC分类号： H01L21/00 , H01L21/764 , H01L49/02 , H01L27/108
CPC分类号： H01L28/88 , H01L21/764 , H01L27/10808 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/90
摘要： A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
摘要翻译：半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

3. 发明授权

US06893982B2 Method for forming a thin film, methods for forming a gate electrode and transistor using the same, and a gate electrode manufactured using the same 有权
标题翻译：用于形成薄膜的方法，用于形成栅电极的方法和使用其的晶体管，以及使用该方法制造的栅电极
公开(公告)号：US06893982B2
公开(公告)日：2005-05-17
申请号：US10337298
申请日：2003-01-07
申请人： Sung-Eui Kim
发明人： Sung-Eui Kim
IPC分类号： H01L21/336 , H01L21/28 , H01L21/316 , H01L21/31
CPC分类号： H01L21/0217 , H01L21/0223 , H01L21/28247 , H01L21/31662
摘要： A method for forming a thin film on a gate electrode reduces oxidation of the gate electrode during a re-oxidation process to fix the damage to the gate oxide film caused during the formation of the gate electrode pattern. The gate electrode pattern formed in this manner will have reduced defects after re-oxidation. After a gate oxide film is formed on a substrate, a gate electrode pattern is formed on the gate oxide film through an etching process. A thin film that includes nitride is then continuously formed on the gate oxide film and on the gate electrode by utilizing a deposition rate difference between the thin film on the gate oxide film and on the thin film forming the gate electrode. Because of the thin film formed on the gate electrode, oxidation of the gate electrode is reduced during the re-oxidation of the gate oxide film.
摘要翻译：在栅电极上形成薄膜的方法减少了在再氧化过程期间栅电极的氧化，以固定在形成栅极电极图形期间引起的栅极氧化膜的损伤。以这种方式形成的栅电极图案将在再氧化后具有减小的缺陷。在基板上形成栅极氧化膜之后，通过蚀刻工艺在栅极氧化膜上形成栅电极图案。然后通过利用栅极氧化膜上的薄膜和形成栅电极的薄膜之间的沉积速率差，在栅极氧化膜和栅电极上连续地形成包括氮化物的薄膜。由于在栅电极上形成薄膜，在栅极氧化膜的再氧化期间，栅电极的氧化降低。

4. 发明授权

US07387943B2 Method for forming layer for trench isolation structure 失效
标题翻译：沟槽隔离结构层形成方法
公开(公告)号：US07387943B2
公开(公告)日：2008-06-17
申请号：US10083756
申请日：2002-02-25
申请人： Do-Hyung Kim , Sung-Eui Kim
发明人： Do-Hyung Kim , Sung-Eui Kim
IPC分类号： H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76224
摘要： A method for forming a thermal oxide layer on the surface of a semiconductor substrate exposed during a semiconductor fabricating process. The thermal oxide layer is to be thin to minimize silicon substrate defects caused by volume expansion. A chemical vapor deposition (CVD) layer is then formed on the thin thermal oxide layer, creating a required thickness. The thin thermal oxide layer and the CVD material layer are formed in the same CVD apparatus. As a result, a process can be simplified and a particle-leading pollution can be prevented.
摘要翻译：一种在半导体制造工艺中暴露的半导体衬底的表面上形成热氧化层的方法。热氧化层应该是薄的，以最小化由体积膨胀引起的硅衬底缺陷。然后在薄的热氧化物层上形成化学气相沉积（CVD）层，产生所需的厚度。在相同的CVD装置中形成薄的热氧化物层和CVD材料层。结果，可以简化工艺，并且可以防止颗粒导致的污染。

5. 发明授权

US06914316B2 Semiconductor trench isolation structure 有权
标题翻译：半导体沟槽隔离结构
公开(公告)号：US06914316B2
公开(公告)日：2005-07-05
申请号：US10617742
申请日：2003-07-14
申请人： Eun-Jung Yun , Sung-Eui Kim
发明人： Eun-Jung Yun , Sung-Eui Kim
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L29/00
CPC分类号： H01L21/76229
摘要： A trench structure of a semiconductor device includes first and second regions of a substrate having first and second trenches, respectively, the first trench having an aspect ratio larger than that of the second trench, a first insulation material on a bottom and sidewalls of the first trench forming a first sub-trench in the first trench, a second insulation material completely filling the first sub-trench, a third insulation material formed on a bottom and sidewalls of the second trench forming a second sub-trench in the second trench, a fourth insulation material formed on a bottom and sidewalls of the second sub-trench, and a fifth insulation material completely filling a third sub-trench formed in the second sub-trench by the fourth insulation material.
摘要翻译：半导体器件的沟槽结构包括分别具有第一和第二沟槽的衬底的第一和第二区域，第一沟槽的纵横比分别大于第二沟槽的纵横比，第一绝缘材料位于第一和第二沟槽的底部和侧壁上在所述第一沟槽中形成第一子沟槽的沟槽，完全填充所述第一子沟槽的第二绝缘材料，形成在所述第二沟槽的底部和侧壁上的第三绝缘材料，所述第二沟槽在所述第二沟槽中形成第二子沟槽，第四绝缘材料形成在第二子沟槽的底部和侧壁上，第五绝缘材料通过第四绝缘材料完全填充形成在第二子沟槽中的第三子沟槽。

6. 发明授权

US06794263B1 Method of manufacturing a semiconductor device including alignment mark 有权
标题翻译：制造包括对准标记的半导体器件的方法
公开(公告)号：US06794263B1
公开(公告)日：2004-09-21
申请号：US10367931
申请日：2003-02-19
申请人： Kong-Soo Lee , Young-Wook Park , Jae-Jong Han , Gi-Hyun Hwang , Kyoung-Seok Kim , Sung-Eui Kim , Seung-Mok Shin
发明人： Kong-Soo Lee , Young-Wook Park , Jae-Jong Han , Gi-Hyun Hwang , Kyoung-Seok Kim , Sung-Eui Kim , Seung-Mok Shin
IPC分类号： H01L2176
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/76229 , H01L2223/54453 , H01L2924/0002 , Y10S438/959 , Y10S438/975 , H01L2924/00
摘要： A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.
摘要翻译：在半导体器件的制造期间抑制半导体衬底上的凹坑产生的方法包括在半导体衬底中形成使用浅沟槽隔离（STI）方法的隔离，在具有隔离的半导体衬底的整个表面上形成绝缘层，使用绝缘层作为缓冲层将离子注入到半导体衬底中，使用快速热退火（RTA）工艺对半导体衬底进行退火，在绝缘层上形成光致抗蚀剂层，然后在光刻胶层中形成开口以暴露底层通过在开口处蚀刻底层形成对准键，以及去除光致抗蚀剂层和绝缘层。或者，可以减小绝缘层的厚度，以防止在半导体衬底的有源区域上出现凹坑。

7. 发明授权

US07714325B2 Trench isolation structure 失效
标题翻译：沟槽隔离结构
公开(公告)号：US07714325B2
公开(公告)日：2010-05-11
申请号：US11748386
申请日：2007-05-14
申请人： Do-Hyung Kim , Sung-Eui Kim
发明人： Do-Hyung Kim , Sung-Eui Kim
IPC分类号： H01L29/12 , H01L29/00
CPC分类号： H01L21/76224
摘要： A method for forming a thermal oxide layer on the surface of a semiconductor substrate exposed during a semiconductor fabricating process. The thermal oxide layer is to be thin to minimize silicon substrate defects caused by volume expansion. A chemical vapor deposition (CVD) layer is then formed on the thin thermal oxide layer, creating a required thickness. The thin thermal oxide layer and the CVD material layer are formed in the same CVD apparatus. As a result, a process can be simplified and a particle-leading pollution can be prevented.
摘要翻译：一种在半导体制造工艺中暴露的半导体衬底的表面上形成热氧化层的方法。热氧化层应该是薄的，以最小化由体积膨胀引起的硅衬底缺陷。然后在薄的热氧化物层上形成化学气相沉积（CVD）层，产生所需的厚度。在相同的CVD装置中形成薄的热氧化物层和CVD材料层。结果，可以简化工艺，并且可以防止颗粒导致的污染。

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