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1. 发明申请

US20070042582A1 Method of forming a nanowire and method of manufacturing a semiconductor device using the same 有权
标题翻译：形成纳米线的方法和使用该纳米线的半导体器件的制造方法
公开(公告)号：US20070042582A1
公开(公告)日：2007-02-22
申请号：US11431216
申请日：2006-05-10
申请人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
发明人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/465
CPC分类号： H01L21/3083 , B82Y10/00 , B82Y30/00 , H01L29/0665 , H01L29/0673 , Y10S977/938
摘要： In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire is formed, and additionally covers a second region of the substrate connected to the first region. An opening is formed by etching an exposed portion of the substrate by the insulation layer pattern. A spacer is formed on sidewalls of the opening and the insulation layer pattern. The nanowire connected to the second region is formed by anisotropically etching a portion of the substrate exposed by the opening until a portion of the insulation layer pattern formed in the trench is exposed.
摘要翻译：在半导体器件中形成纳米线的方法中，通过部分蚀刻体半导体衬底形成沟槽。在衬底上形成绝缘层图案以填充沟槽。绝缘层图案覆盖形成有纳米线的基板的第一区域，并且另外覆盖连接到第一区域的基板的第二区域。通过用绝缘层图案蚀刻衬底的暴露部分形成开口。在开口和绝缘层图案的侧壁上形成间隔物。连接到第二区域的纳米线通过各向异性蚀刻由开口暴露的基板的一部分，直到形成在沟槽中的绝缘层图案的一部分露出来形成。

2. 发明授权

US07410853B2 Method of forming a nanowire and method of manufacturing a semiconductor device using the same 有权
标题翻译：形成纳米线的方法和使用该纳米线的半导体器件的制造方法
公开(公告)号：US07410853B2
公开(公告)日：2008-08-12
申请号：US11431216
申请日：2006-05-10
申请人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
发明人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/3083 , B82Y10/00 , B82Y30/00 , H01L29/0665 , H01L29/0673 , Y10S977/938
摘要： In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire is formed, and additionally covers a second region of the substrate connected to the first region. An opening is formed by etching an exposed portion of the substrate by the insulation layer pattern. A spacer is formed on sidewalls of the opening and the insulation layer pattern. The nanowire connected to the second region is formed by anisotropically etching a portion of the substrate exposed by the opening until a portion of the insulation layer pattern formed in the trench is exposed.
摘要翻译：在半导体器件中形成纳米线的方法中，通过部分蚀刻体半导体衬底形成沟槽。在衬底上形成绝缘层图案以填充沟槽。绝缘层图案覆盖形成有纳米线的基板的第一区域，并且另外覆盖连接到第一区域的基板的第二区域。通过用绝缘层图案蚀刻衬底的暴露部分形成开口。在开口和绝缘层图案的侧壁上形成间隔物。连接到第二区域的纳米线通过各向异性蚀刻由开口暴露的基板的一部分，直到形成在沟槽中的绝缘层图案的一部分露出而形成。

3. 发明授权

US07358142B2 Method for forming a FinFET by a damascene process 有权
标题翻译：通过镶嵌工艺形成FinFET的方法
公开(公告)号：US07358142B2
公开(公告)日：2008-04-15
申请号：US11046623
申请日：2005-01-28
申请人： Hee-Soo Kang , Chul Lee , Tae-Yong Kim , Dong-Gun Park , Young-Joon Ahn , Choong-Ho Lee , Sang-Yeon Han
发明人： Hee-Soo Kang , Chul Lee , Tae-Yong Kim , Dong-Gun Park , Young-Joon Ahn , Choong-Ho Lee , Sang-Yeon Han
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.
摘要翻译：使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。源区和漏区形成在没有形成栅电极的有源区的剩余部分上。栅电极分离变得足够，并且可以降低制造成本。

4. 发明申请

US20050170593A1 Method for forming a FinFET by a damascene process 有权
标题翻译：通过镶嵌工艺形成FinFET的方法
公开(公告)号：US20050170593A1
公开(公告)日：2005-08-04
申请号：US11046623
申请日：2005-01-28
申请人： Hee-Soo Kang , Chul Lee , Tae-Yong Kim , Dong-Gun Park , Young-Joon Ahn , Choong-Ho Lee , Sang-Yeon Han
发明人： Hee-Soo Kang , Chul Lee , Tae-Yong Kim , Dong-Gun Park , Young-Joon Ahn , Choong-Ho Lee , Sang-Yeon Han
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8228 , H01L29/786 , H01M8/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.
摘要翻译：使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。源极和漏极区域形成在没有形成栅电极的有源区的剩余部分上。栅电极分离变得足够，并且可以降低制造成本。

5. 发明授权

US07323375B2 Fin field effect transistor device and method of fabricating the same 失效
标题翻译： Fin场效应晶体管器件及其制造方法
公开(公告)号：US07323375B2
公开(公告)日：2008-01-29
申请号：US11091457
申请日：2005-03-28
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L21/84 , H01L29/66795
摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.
摘要翻译：形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。鳍形半导体有源区域的至少上部被牺牲层覆盖。该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。电绝缘区域形成在牺牲间隔物上。然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

6. 发明授权

US07227220B2 Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效
标题翻译：具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法
公开(公告)号：US07227220B2
公开(公告)日：2007-06-05
申请号：US11240544
申请日：2005-09-30
申请人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
发明人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.
摘要翻译：半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触以及与第一线成直角形成并覆盖沟道区的字线。

7. 发明授权

US07160780B2 Method of manufacturing a fin field effect transistor 有权
标题翻译：制造鳍式场效应晶体管的方法
公开(公告)号：US07160780B2
公开(公告)日：2007-01-09
申请号：US11066703
申请日：2005-02-23
申请人： Chul Lee , Jae-Man Yoon , Choong-Ho Lee
发明人： Chul Lee , Jae-Man Yoon , Choong-Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795
摘要： In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of the fin active region, along a line shape that at least one time crosses with the fin active region, thus forming a trench. The fin active region is exposed by the trench and thereon a gate insulation layer is formed. Thereby, productivity is increased and performance of the device is improved. A fin FET employs a bulk silicon substrate of which a manufacturing cost is lower than that of a conventional SOI type silicon substrate. Also, a floating body effect can be prevented, or is substantially reduced.
摘要翻译：在一个示例性实施例中，翅片有源区域沿着整体形成浅沟槽绝缘体的体硅基板沿着一个方向突出，以覆盖翅片有源区域。去除浅沟槽绝缘体，以沿着至少一次与翅片有源区交叉的线形状选择性地暴露翅片有源区的上部和侧壁，从而形成沟槽。翅片有源区域被沟槽暴露，并且形成有栅极绝缘层。从而，提高了生产效率并提高了设备的性能。翅片FET采用其制造成本低于常规SOI型硅衬底的制造成本的体硅衬底。此外，可以防止浮体效应或大大降低浮体效应。

8. 发明申请

US20050269629A1 Fin field effect transistors and methods of fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20050269629A1
公开(公告)日：2005-12-08
申请号：US11084922
申请日：2005-03-21
申请人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
发明人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
IPC分类号： H01L21/00 , H01L21/20 , H01L21/265 , H01L21/336 , H01L21/84 , H01L29/76 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L21/26513 , H01L21/845 , H01L29/66795 , H01L29/78624
摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.
摘要翻译：翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。翅片在基底上并沿着和垂直方向横向延伸。栅电极覆盖翅片的一侧和顶部。栅绝缘层位于栅电极和鳍之间。翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。翅片的源极区域具有与鳍片的漏极区域不同的宽度。

9. 发明申请

US20050250285A1 Fin field effect transistor device and method of fabricating the same 失效
标题翻译： Fin场效应晶体管器件及其制造方法
公开(公告)号：US20050250285A1
公开(公告)日：2005-11-10
申请号：US11091457
申请日：2005-03-28
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L29/786 , H01L29/94
CPC分类号： H01L29/7851 , H01L21/84 , H01L29/66795
摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.
摘要翻译：形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。鳍形半导体有源区域的至少上部被牺牲层覆盖。该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。电绝缘区域形成在牺牲间隔物上。然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

10. 发明授权

US07883972B2 Semiconductor device having a fin structure and method of manufacturing the same 失效
标题翻译：具有翅片结构的半导体器件及其制造方法
公开(公告)号：US07883972B2
公开(公告)日：2011-02-08
申请号：US12219984
申请日：2008-07-31
申请人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
发明人： Jae-Man Yoon , Choong-Ho Lee , Chul Lee , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.
摘要翻译：半导体器件可以包括具有连接在源极/漏极图案之间的源极/漏极区域和沟道鳍片的鳍结构。栅极绝缘层可以设置在通道散热片上。栅电极可以包括下栅极图案和上栅极图案。下栅极图案可以在垂直方向上延伸并接触栅极绝缘层。上栅极图案可以在基本上垂直于第一水平方向的第二水平方向上延伸。上栅极图案可以连接到下栅极图案的上部。

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