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1. 发明授权

US08837197B2 Circuit for generating write signal, variable resistance memory device, and method for programming variable resistance memory 有权
标题翻译：用于产生写入信号的电路，可变电阻存储器件以及编程可变电阻存储器的方法
公开(公告)号：US08837197B2
公开(公告)日：2014-09-16
申请号：US13369361
申请日：2012-02-09
申请人： Young-Hoon Oh , Young-Don Choi , Ick-Hyun Song
发明人： Young-Hoon Oh , Young-Don Choi , Ick-Hyun Song
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0076 , G11C2013/0092
摘要： A circuit for generating a write signal includes a pre-emphasis signal generator that receives location information of a to-be-programmed memory cell and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell, and a write driver that generates a program signal corresponding to data to be programmed in the to-be-programmed memory cell. A write signal is generated by combining the program signal with the pre-emphasis signal supplied from the pre-emphasis signal generator, and the write signal output to the to-be-programmed memory cell.
摘要翻译：用于产生写信号的电路包括预加重信号发生器，其接收待编程存储器单元的位置信息，并根据待编程存储器单元的位置信息产生预加重信号;以及写入驱动器，其产生与要编程的存储器单元中要编程的数据相对应的程序信号。通过将编程信号与从预加重信号发生器提供的预加重信号组合，并将写入信号输出到被编程的存储单元，产生写入信号。

2. 发明授权

US08605517B2 Variable resistance memory devices using read mirror currents 有权
标题翻译：使用读反射镜电流的可变电阻存储器件
公开(公告)号：US08605517B2
公开(公告)日：2013-12-10
申请号：US13346377
申请日：2012-01-09
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C11/16 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C2013/0045
摘要： A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current at a second signal node responsive to the cell current and to generate an output signal indicative of a state of the variable resistance memory element responsive to a voltage at the second signal node.
摘要翻译：非易失性存储器件包括可变电阻存储器元件和在第一信号节点处耦合到可变电阻存储器元件的读取电路，并且被配置为经由第一信号节点向可变电阻存储器元件提供读取电流，以提供镜响应于电池电流在第二信号节点处的电流，并响应于第二信号节点处的电压产生指示可变电阻存储元件的状态的输出信号。

3. 发明授权

US07768849B2 Semiconductor memory device capable of optimizing signal transmission power and power initializing method thereof 有权
标题翻译：能够优化信号传输功率和功率初始化方法的半导体存储器件
公开(公告)号：US07768849B2
公开(公告)日：2010-08-03
申请号：US12106175
申请日：2008-04-18
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： G11C29/00
CPC分类号： G11C7/20 , G11C5/02 , G11C5/04 , G11C5/063 , G11C5/14 , G11C29/02 , G11C29/021 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first chip, checking whether the test signal provided to the first chip has an error, providing the checking result to the signal-providing chip, setting the power of a first signal provided to the first chip according to the checking result, and setting the power of a signal provided to a second chip adjacent to the first chip and close to the signal-providing chip using the power of the first signal.
摘要翻译：半导体存储器件可以基于无线信号传输自动控制芯片上的信号传输功率。半导体存储器件可以具有多芯片堆叠结构。半导体存储器件的功率初始化方法可以包括向第一芯片提供由信号提供芯片产生的测试信号，检查提供给第一芯片的测试信号是否具有错误，为检测结果提供信号提供根据检查结果设置提供给第一芯片的第一信号的功率，并且设置提供给与第一芯片相邻的第二芯片并且靠近信号提供芯片的信号的功率，使用第一个信号。

4. 发明申请

US20090127668A1 STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SERIAL PATH THEREOF 有权
标题翻译：堆叠式半导体器件及其串联路径的形成方法
公开(公告)号：US20090127668A1
公开(公告)日：2009-05-21
申请号：US12274134
申请日：2008-11-19
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： H01L23/50 , H01L21/60
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/06 , H01L24/14 , H01L24/17 , H01L2224/0401 , H01L2224/0615 , H01L2224/1416 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/01021 , H01L2924/01033 , H01L2924/01058 , H01L2924/01082 , H01L2924/01322 , H01L2924/30107
摘要： A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other. According to the stacked semiconductor device and method, a plurality of chips having the same pattern are rotated about the center of the chips and stacked, so that a parallel path and a serial path can be formed.
摘要翻译：提供叠层半导体器件和形成层叠半导体器件的串行路径的方法。叠层半导体器件包括多个芯片，每个芯片具有用于接收输入信号的第一内部电路，执行指定的操作并输出输出信号。每个芯片包括设置在每个芯片的一个表面上的相同位置处的串行凸块，接收输入信号并将输入信号传送到第一内部电路，以及串联穿通硅通孔（TSV）相对于芯片的中心与串联凸起对称的位置以穿透芯片，以及接收和传送输出信号。这里，芯片交替地旋转和堆叠，使得相邻芯片的串行TSV和串联凸块彼此接触。根据叠层半导体器件和方法，具有相同图案的多个芯片围绕芯片的中心旋转并堆叠，从而可以形成平行路径和串行路径。

5. 发明授权

US08723529B2 Semiconductor device, test method, and test apparatus 有权
标题翻译：半导体器件，测试方法和测试仪器
公开(公告)号：US08723529B2
公开(公告)日：2014-05-13
申请号：US13270383
申请日：2011-10-11
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2884 , G01R31/2879 , G11C13/0004 , G11C29/12005 , G11C29/1201 , G11C29/48 , G11C2029/5006
摘要： A semiconductor device includes; a first pad that receives an external voltage during a test, a second pad coupled to an external impedance during the test, a voltage-current converter coupled to the first pad and the second pad and generating a bias current substantially in response to only the external voltage and the external impedance, and an internal circuit responsive to a test current during the test, such that the level of the test current is defined by the level of the bias current.
摘要翻译：一种半导体器件包括：在测试期间接收外部电压的第一焊盘，在测试期间耦合到外部阻抗的第二焊盘，耦合到第一焊盘和第二焊盘的电压 - 电流转换器，并且基本上仅响应于外部产生偏置电流电压和外部阻抗，以及响应于测试期间的测试电流的内部电路，使得测试电流的电平由偏置电流的电平定义。

6. 发明授权

US08130573B2 Semiconductor memory device capable of optimizing signal transmission power and power initializing method thereof 有权
标题翻译：能够优化信号传输功率和功率初始化方法的半导体存储器件
公开(公告)号：US08130573B2
公开(公告)日：2012-03-06
申请号：US12838757
申请日：2010-07-19
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： G11C29/00
CPC分类号： G11C7/20 , G11C5/02 , G11C5/04 , G11C5/063 , G11C5/14 , G11C29/02 , G11C29/021 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first chip, checking whether the test signal provided to the first chip has an error, providing the checking result to the signal-providing chip, setting the power of a first signal provided to the first chip according to the checking result, and setting the power of a signal provided to a second chip adjacent to the first chip and close to the signal-providing chip using the power of the first signal.
摘要翻译：半导体存储器件可以基于无线信号传输自动控制芯片上的信号传输功率。半导体存储器件可以具有多芯片堆叠结构。半导体存储器件的功率初始化方法可以包括向第一芯片提供由信号提供芯片产生的测试信号，检查提供给第一芯片的测试信号是否具有错误，为检测结果提供信号提供根据检查结果设置提供给第一芯片的第一信号的功率，并且设置提供给与第一芯片相邻的第二芯片并且靠近信号提供芯片的信号的功率，使用第一个信号。

7. 发明授权

US09165893B2 Semiconductor device including coupling conductive pattern 有权
标题翻译：半导体器件包括耦合导电图案
公开(公告)号：US09165893B2
公开(公告)日：2015-10-20
申请号：US13229193
申请日：2011-09-09
申请人： Yong-Hoon Kim , Jong-Joo Lee , Sang-Youb Lee , Young-Don Choi , Hee-Seok Lee
发明人： Yong-Hoon Kim , Jong-Joo Lee , Sang-Youb Lee , Young-Don Choi , Hee-Seok Lee
IPC分类号： H04B5/00 , H01L23/64 , H01L25/10 , H01L23/00
CPC分类号： H01L23/645 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06558 , H01L2225/1023 , H01L2924/00014 , H01L2924/01019 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H01L2924/3511 , H04B5/0012 , H04B5/0031 , H04B5/0037 , H04B5/0075 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.
摘要翻译：公开了一种包括通孔的半导体器件。半导体器件可以包括第一半导体芯片，其包括形成在第一表面上的收发器电路，形成在与第一表面相对的第二表面上的第一耦合导体图案，以及连接收发器电路和第一耦合导电模式。可以存在位于第二半导体芯片上的收发器，并且包括面向与第一耦合导电图案无线通信的第一耦合导电图案的第二耦合导电图案。

8. 发明申请

US20120176830A1 VARIABLE RESISTANCE MEMORY DEVICES USING READ MIRROR CURRENTS 有权
标题翻译：使用READ MIRROR电流的可变电阻存储器件
公开(公告)号：US20120176830A1
公开(公告)日：2012-07-12
申请号：US13346377
申请日：2012-01-09
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/22 , G11C11/16 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C2013/0045
摘要： A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current at a second signal node responsive to the cell current and to generate an output signal indicative of a state of the variable resistance memory element responsive to a voltage at the second signal node.
摘要翻译：非易失性存储器件包括可变电阻存储器元件和在第一信号节点处耦合到可变电阻存储器元件的读取电路，并且被配置为经由第一信号节点向可变电阻存储器元件提供读取电流，以提供镜响应于电池电流在第二信号节点处的电流，并响应于第二信号节点处的电压产生指示可变电阻存储元件的状态的输出信号。

9. 发明授权

US07816776B2 Stacked semiconductor device and method of forming serial path thereof 有权
标题翻译：叠层半导体器件及其串联路径的形成方法
公开(公告)号：US07816776B2
公开(公告)日：2010-10-19
申请号：US12274134
申请日：2008-11-19
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： H01L23/02 , H01L21/00
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/06 , H01L24/14 , H01L24/17 , H01L2224/0401 , H01L2224/0615 , H01L2224/1416 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/01021 , H01L2924/01033 , H01L2924/01058 , H01L2924/01082 , H01L2924/01322 , H01L2924/30107
摘要： A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other. According to the stacked semiconductor device and method, a plurality of chips having the same pattern are rotated about the center of the chips and stacked, so that a parallel path and a serial path can be formed.
摘要翻译：提供叠层半导体器件和形成层叠半导体器件的串行路径的方法。叠层半导体器件包括多个芯片，每个芯片具有用于接收输入信号的第一内部电路，执行指定的操作并输出输出信号。每个芯片包括设置在每个芯片的一个表面上的相同位置处的串行凸块，接收输入信号并将输入信号传送到第一内部电路，以及串联穿通硅通孔（TSV）相对于芯片的中心与串联凸起对称的位置以穿透芯片，以及接收和传送输出信号。这里，芯片交替地旋转和堆叠，使得相邻芯片的串行TSV和串联凸块彼此接触。根据叠层半导体器件和方法，具有相同图案的多个芯片围绕芯片的中心旋转并堆叠，从而可以形成平行路径和串行路径。

10. 发明申请

US20100225364A1 Stacked semiconductor devices and signal distribution methods thereof 有权
标题翻译：叠层半导体器件及其信号分配方法
公开(公告)号：US20100225364A1
公开(公告)日：2010-09-09
申请号：US12801012
申请日：2010-05-17
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： H03K3/00 , H05K1/18 , H01L23/538
CPC分类号： H01L25/0657 , G06F1/10 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique.
摘要翻译：堆叠的半导体器件包括多个堆叠的芯片，每个堆叠的芯片具有用于接收信号的多个元件。用于接收信号的至少一个第一梯形主信号线布置成通过芯片。至少一个第二梯形图主信号线被布置成穿过芯片。多个梯形缓冲器将从第一梯形图主信号线施加的信号缓冲到第二梯形图主信号线。使用梯形电路网络技术将信号均匀分布到堆叠芯片。

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