专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08837197B2 Circuit for generating write signal, variable resistance memory device, and method for programming variable resistance memory 有权
标题翻译：用于产生写入信号的电路，可变电阻存储器件以及编程可变电阻存储器的方法
公开(公告)号：US08837197B2
公开(公告)日：2014-09-16
申请号：US13369361
申请日：2012-02-09
申请人： Young-Hoon Oh , Young-Don Choi , Ick-Hyun Song
发明人： Young-Hoon Oh , Young-Don Choi , Ick-Hyun Song
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0076 , G11C2013/0092
摘要： A circuit for generating a write signal includes a pre-emphasis signal generator that receives location information of a to-be-programmed memory cell and generates a pre-emphasis signal depending on the location information of the to-be-programmed memory cell, and a write driver that generates a program signal corresponding to data to be programmed in the to-be-programmed memory cell. A write signal is generated by combining the program signal with the pre-emphasis signal supplied from the pre-emphasis signal generator, and the write signal output to the to-be-programmed memory cell.
摘要翻译：用于产生写信号的电路包括预加重信号发生器，其接收待编程存储器单元的位置信息，并根据待编程存储器单元的位置信息产生预加重信号;以及写入驱动器，其产生与要编程的存储器单元中要编程的数据相对应的程序信号。通过将编程信号与从预加重信号发生器提供的预加重信号组合，并将写入信号输出到被编程的存储单元，产生写入信号。

2. 发明授权

US08189417B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08189417B2
公开(公告)日：2012-05-29
申请号：US13188728
申请日：2011-07-22
申请人： Young-Hoon Oh , Sung-Yeon Lee
发明人： Young-Hoon Oh , Sung-Yeon Lee
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , G11C7/04 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/1697
摘要： A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation.
摘要翻译：半导体存储器件使用磁性隧道结器件（MTJ）并且包括连接在第一驱动线和第二驱动线之间的存储单元，并被配置为存储具有基于流过的电流的方向确定的数据状态的数据第一驱动线和第二驱动线，以及电流控制块，被配置为响应于写入操作中的温度信息来控制提供给第一和第二驱动线的电源电流。

3. 发明申请

US20120029644A1 Compliant Interbody Fusion Device with Deployable Bone Anchors 审中-公开
标题翻译：符合标准的体内融合装置与可部署的骨锚
公开(公告)号：US20120029644A1
公开(公告)日：2012-02-02
申请号：US13267869
申请日：2011-10-06
申请人： Aaron D. Markworth , Young Hoon Oh , Mahmoud F. Abdelgany
发明人： Aaron D. Markworth , Young Hoon Oh , Mahmoud F. Abdelgany
IPC分类号： A61F2/44
CPC分类号： A61F2/447 , A61F2/4611 , A61F2002/30364 , A61F2002/30476 , A61F2002/30523 , A61F2002/30576 , A61F2002/30579 , A61F2002/30598 , A61F2002/30772 , A61F2002/30841 , A61F2002/30904 , A61F2002/4475 , A61F2002/4627 , A61F2220/0025 , A61F2220/0033
摘要： An interbody fusion implant with deployable bone anchors includes a support member, a monolithic body that accommodates the support member, and a longitudinal hole along a vertical length of the support member. The support member includes a first end and a second end. The second end includes two flanges. The flanges are configured to dig into an endplate of a vertebral body. The flanges of the support member provide a location fixation on an implantation of the interbody fusion implant into the vertebral body. The support member may also include at least one of a clip shaped support member and an I-shaped support member. The I-shaped support member may allow a rigidity and a support in flexion-extension through a living-hinge positioned in a middle of the I-shaped support member. The longitudinal hole sustains loads imported on the interbody fusion implant and allows the interbody fusion implant to flex freely.
摘要翻译：具有可展开的骨锚的体间融合植入物包括支撑构件，容纳支撑构件的整体，以及沿着支撑构件的垂直长度的纵向孔。支撑构件包括第一端和第二端。第二端包括两个法兰。凸缘被配置成挖入椎体的终板。支撑构件的凸缘提供了将椎体间融合植入物植入椎体中的位置固定。支撑构件还可以包括夹形支撑构件和I形支撑构件中的至少一个。 I形支撑构件可以允许通过位于I形支撑构件的中间的活动铰链弯曲延伸的刚性和支撑。纵向孔保持进入体内融合植入物的载荷，并允许椎间融合植入物自由弯曲。

4. 发明申请

US20110280062A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110280062A1
公开(公告)日：2011-11-17
申请号：US13188728
申请日：2011-07-22
申请人： Young-Hoon Oh , Sung-Yeon Lee
发明人： Young-Hoon Oh , Sung-Yeon Lee
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C7/04 , G11C11/1655 , G11C11/1659 , G11C11/1675 , G11C11/1697
摘要： A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation.
摘要翻译：半导体存储器件使用磁性隧道结器件（MTJ），并且包括连接在第一驱动线和第二驱动线之间的存储单元，并被配置为存储具有基于流过的电流的方向确定的数据状态的数据第一驱动线和第二驱动线，以及电流控制块，被配置为响应于写入操作中的温度信息来控制提供给第一和第二驱动线的电源电流。

5. 发明授权

US08059480B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08059480B2
公开(公告)日：2011-11-15
申请号：US12488632
申请日：2009-06-22
申请人： Sung-Yeon Lee , Young-Hoon Oh
发明人： Sung-Yeon Lee , Young-Hoon Oh
IPC分类号： G11C7/02
CPC分类号： G11C11/4099 , G11C5/147 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate a reference current corresponding to each of the memory cells; and a sense amplification unit configured to sense and amplify the reference current and a data current corresponding to a memory cell connected to an activated word line among the word lines.
摘要翻译：半导体存储器件包括配置为对应于用于存储数据的多个字线中的每一个的多个存储器单元; 多个参考存储单元，被配置为包括第一和第二磁存储器件，其下电极彼此共同连接，以产生与每个存储单元相对应的参考电流; 以及感测放大单元，被配置为感测和放大参考电流以及与连接到字线之间的激活字线的存储单元相对应的数据电流。

6. 发明授权

US07944258B2 Semiconductor integrated circuit including delay line of delay locked loop and method of controlling delay time using the same 有权
标题翻译：半导体集成电路包括延迟锁定回路的延迟线和使用其延迟时间的控制方法
公开(公告)号：US07944258B2
公开(公告)日：2011-05-17
申请号：US11647467
申请日：2006-12-29
申请人： Young-Hoon Oh
发明人： Young-Hoon Oh
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A semiconductor integrated circuit includes a delay line of a delay locked loop. The delay line of the delay locked loop includes a delay variation detecting unit that outputs a detection signal according to a variation in delay time using a reference clock signal, and a plurality of delay units that change a delay time according to the detection signal and delay the output of an input signal by the changed delay time.
摘要翻译：半导体集成电路包括延迟锁定环路的延迟线。延迟锁定环路的延迟线包括延迟变化检测单元，其使用参考时钟信号根据延迟时间的变化输出检测信号，以及多个延迟单元，其根据检测信号和延迟来改变延迟时间通过改变的延迟时间输出一个输入信号。

7. 发明授权

US07733141B2 Semiconductor device and operating method thereof 失效
标题翻译：半导体器件及其操作方法
公开(公告)号：US07733141B2
公开(公告)日：2010-06-08
申请号：US12217002
申请日：2008-06-30
申请人： Young-Hoon Oh
发明人： Young-Hoon Oh
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0812 , H03L7/093
摘要： A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.
摘要翻译：半导体器件的延迟锁定环（DLL）具有相对小的面积和低的电流消耗，同时具有校正占空比的功能。所述半导体器件包括分配单元，其被配置为接收和分离参考时钟以输出对应于所述参考时钟的第一边缘的第一时钟和对应于第二边缘的第二时钟;电压生成单元，被配置为产生对应于对应于第一时钟的占空比和对应于第二时钟的占空比的第二电压，电压比较单元，被配置为将第一和第二电压的电平彼此进行比较;以及时钟延迟单元，被配置为接收用于响应于电压比较单元的输出信号来确定延迟量的接收时钟的第一和第二时钟。

8. 发明申请

US20100137988A1 Compliant Interbody Fusion Device With Deployable Bone Anchors 有权
标题翻译：具有可部署骨锚的符合标准的体内融合装置
公开(公告)号：US20100137988A1
公开(公告)日：2010-06-03
申请号：US12326079
申请日：2008-12-01
申请人： Aaron D. Markworth , Young Hoon Oh , Mahmoud F. Abdelgany
发明人： Aaron D. Markworth , Young Hoon Oh , Mahmoud F. Abdelgany
IPC分类号： A61F2/44 , A61B17/70 , A61B17/04
CPC分类号： A61F2/447 , A61F2/4611 , A61F2002/30364 , A61F2002/30476 , A61F2002/30523 , A61F2002/30576 , A61F2002/30579 , A61F2002/30598 , A61F2002/30772 , A61F2002/30841 , A61F2002/30904 , A61F2002/4475 , A61F2002/4627 , A61F2220/0025 , A61F2220/0033
摘要： An interbody fusion implant with deployable bone anchors includes a support member, a monolithic body that accommodates the support member, and a longitudinal hole along a vertical length of the support member. The support member includes a first end and a second end. The second end includes two flanges. The flanges are configured to dig into an endplate of a vertebral body. The flanges of the support member provide a location fixation on an implantation of the interbody fusion implant into the vertebral body. The support member may also include at least one of a clip shaped support member and an I-shaped support member. The I-shaped support member may allow a rigidity and a support in flexion-extension through a living-hinge positioned in a middle of the I-shaped support member. The longitudinal hole sustains loads imported on the interbody fusion implant and allows the interbody fusion implant to flex freely.
摘要翻译：具有可展开的骨锚的体间融合植入物包括支撑构件，容纳支撑构件的整体，以及沿着支撑构件的垂直长度的纵向孔。支撑构件包括第一端和第二端。第二端包括两个法兰。凸缘被配置成挖入椎体的终板。支撑构件的凸缘提供了将椎体间融合植入物植入椎体中的位置固定。支撑构件还可以包括夹形支撑构件和I形支撑构件中的至少一个。 I形支撑构件可以允许通过位于I形支撑构件的中间的活动铰链弯曲延伸的刚性和支撑。纵向孔保持进入体内融合植入物的载荷，并允许椎间融合植入物自由弯曲。

9. 发明申请

US20080002514A1 Semiconductor memory device and driving method thereof 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080002514A1
公开(公告)日：2008-01-03
申请号：US11647402
申请日：2006-12-29
申请人： Young-Hoon Oh , Kwang-Myoung Rho
发明人： Young-Hoon Oh , Kwang-Myoung Rho
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1069 , G11C7/22 , G11C7/222 , G11C11/401 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.
摘要翻译：半导体存储器件包括：用于将延迟锁定环（DLL）时钟延迟预定延迟时间的可变延迟，以输出延迟的DLL时钟; 输出驱动器，用于响应于延迟的DLL时钟输出数据和数据选通信号; 以及校准控制器，用于响应于输出AC参数来控制可变延迟的预定延迟时间。

10. 发明申请

US20130015421A1 PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：相变随机访问存储器件及其制造方法
公开(公告)号：US20130015421A1
公开(公告)日：2013-01-17
申请号：US13339691
申请日：2011-12-29
申请人： Joon Seop SIM , Jae Hyun Son , Dae Woong Lee , Young Hoon Oh
发明人： Joon Seop SIM , Jae Hyun Son , Dae Woong Lee , Young Hoon Oh
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase change random access memory (PCRAM) device and method of manufacturing the same are provided. The PCRAM includes bottom electrode contacts formed on a semiconductor substrate that includes a lower structure, phase-change material patterns in contact with the bottom electrode contacts, respectively, and heat insulating units formed between the phase-change material patterns.
摘要翻译：提供了相变随机存取存储器（PCRAM）装置及其制造方法。 PCRAM包括分别形成在包括下部结构的半导体衬底上的底部电极触点和与底部电极触点相接触的相变材料图案，以及形成在相变材料图案之间的绝热单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式