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1. 发明申请

US20080055805A1 SEMICONDUCTOR DEVICE HAVING ELECTRO STATIC DISCHARGE DETECTION CIRCUIT 审中-公开
标题翻译：具有电子静电放电检测电路的半导体器件
公开(公告)号：US20080055805A1
公开(公告)日：2008-03-06
申请号：US11754685
申请日：2007-05-29
申请人： Won-Hyung Pong , Jong-Sung Jeon , Young-Chul Kim
发明人： Won-Hyung Pong , Jong-Sung Jeon , Young-Chul Kim
IPC分类号： H02H9/04 , H02H9/00
CPC分类号： H01L27/0285
摘要： A semiconductor device having an electro static discharge (ESD) protection circuit includes an input/output pad configured to receive a voltage higher than an operating voltage of the semiconductor device and an ESD (electro static discharge) protection circuit configured to protect an internal circuit of the semiconductor device from ESD when ESD occurs at the input/output pad. The ESD protection circuit may include a protection circuit configured to flow the ESD current into an operating voltage line and/or a ground voltage line, an ESD detection circuit configured to detect the ESD current flowing in the operating voltage line, and a control circuit configured to cause the protection circuit to be coupled to, or isolated from, the ground voltage line in response to an output signal of the ESD detection circuit.
摘要翻译：具有静电放电（ESD）保护电路的半导体器件包括被配置为接收高于半导体器件的工作电压的电压的输入/输出焊盘和被配置为保护半导体器件的内部电路的ESD（静电放电）保护电路，当ESD在输入/输出焊盘发生时，半导体器件由ESD产生。 ESD保护电路可以包括保护电路，其配置为将ESD电流流动到工作电压线和/或接地电压线中，ESD检测电路被配置为检测在工作电压线中流动的ESD电流，以及配置的控制电路使得保护电路响应于ESD检测电路的输出信号而耦合到或与隔离电压线隔离。

2. 发明申请

US20060180869A1 Primitive cell that is robust against ESD 有权
公开(公告)号：US20060180869A1
公开(公告)日：2006-08-17
申请号：US11352603
申请日：2006-02-13
申请人： Won-Hyung Pong , Jong-Sung Jeon , Young-Chul Kim
发明人： Won-Hyung Pong , Jong-Sung Jeon , Young-Chul Kim
IPC分类号： H01L29/94
CPC分类号： H01L29/4238 , H01L27/0266
摘要： A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS transistor has a first terminal connected to a high power source, and a gate to which a control voltage is applied and which has a plurality of fingers. The low finger NMOS transistor has a first terminal connected to a low power source, a gate to which the control voltage is applied and which has a plurality of fingers, and a second terminal connected to a second terminal of the PMOS transistor. The number of the fingers of the gate of the NMOS transistor is smaller than the number of fingers of the gate of the PMOS transistor and the length of each of the fingers of the NMOS transistor is greater than the length of each of the fingers of the PMOS transistor.

3. 发明授权

US07622755B2 Primitive cell that is robust against ESD 有权
标题翻译：对抗ESD的抗原细胞
公开(公告)号：US07622755B2
公开(公告)日：2009-11-24
申请号：US11352603
申请日：2006-02-13
申请人： Won-Hyung Pong , Jong-Sung Jeon , Young-Chul Kim
发明人： Won-Hyung Pong , Jong-Sung Jeon , Young-Chul Kim
IPC分类号： H01L21/8238 , H01L29/423 , H01L29/78
CPC分类号： H01L29/4238 , H01L27/0266
摘要： A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS transistor has a first terminal connected to a high power source, and a gate to which a control voltage is applied and which has a plurality of fingers. The low finger NMOS transistor has a first terminal connected to a low power source, a gate to which the control voltage is applied and which has a plurality of fingers, and a second terminal connected to a second terminal of the PMOS transistor. The number of the fingers of the gate of the NMOS transistor is smaller than the number of fingers of the gate of the PMOS transistor and the length of each of the fingers of the NMOS transistor is greater than the length of each of the fingers of the PMOS transistor.
摘要翻译：提供了一种具有耐ESD性能的栅格图案的原始单元。原始单元包括：高指状PMOS晶体管和低指状NMOS晶体管。高指PMOS晶体管具有连接到高功率源的第一端子和施加控制电压且具有多个指状物的栅极。低指状NMOS晶体管具有连接到低功率源的第一端子，施加控制电压的栅极，并且具有多个指状物，以及连接到PMOS晶体管的第二端子的第二端子。 NMOS晶体管的栅极的指状数小于PMOS晶体管的栅极的指状数，并且NMOS晶体管的每个指状物的长度大于每个的指状物的长度 PMOS晶体管。

4. 发明申请

US20060249792A1 Electrostatic discharge protection circuit and integrated circuit having the same 审中-公开
标题翻译：静电放电保护电路和集成电路具有相同的功能
公开(公告)号：US20060249792A1
公开(公告)日：2006-11-09
申请号：US11415040
申请日：2006-05-01
申请人： Young-Chul Kim , Jong-Sung Jeon , Won-Hyung Pong
发明人： Young-Chul Kim , Jong-Sung Jeon , Won-Hyung Pong
IPC分类号： H01L23/62
CPC分类号： H01L27/0262
摘要： An electrostatic discharge (ESD) protection circuit has a low trigger voltage. The ESD protection circuit is coupled between two rails. The ESD protection circuit includes a connection load and a second transistor. The connection load turns on a first transistor when an ESD event occurs, and the second transistor generates a current due to an avalanche breakdown. A latch-up current is generated due to the avalanche breakdown.
摘要翻译：静电放电（ESD）保护电路具有低触发电压。 ESD保护电路耦合在两个导轨之间。 ESD保护电路包括连接负载和第二晶体管。当ESD事件发生时，连接负载导通第一晶体管，并且第二晶体管由于雪崩击穿而产生电流。由于雪崩击穿而产生闭锁电流。

5. 发明授权

US06835624B2 Semiconductor device for protecting electrostatic discharge and method of fabricating the same 有权
标题翻译：用于保护静电放电的半导体装置及其制造方法
公开(公告)号：US06835624B2
公开(公告)日：2004-12-28
申请号：US10384833
申请日：2003-03-10
申请人： Won-Hyung Pong , Hyung-Rae Park
发明人： Won-Hyung Pong , Hyung-Rae Park
IPC分类号： H01L218238
CPC分类号： H01L29/66659 , H01L29/7835
摘要： In a semiconductor device for protecting an electrostatic discharge and a method of fabricating the same, a gate electrode is disposed on a semiconductor substrate of first conductivity type, and a heavily doped region and a vertical lightly doped region surround the heavily doped region. The heavily doped region and vertical lightly doped region have a second conductivity type and are disposed in the semiconductor substrate on both sides of the gate electrode. The vertical lightly doped region has a lower impurity concentration and a larger depth than the heavily doped regions. A horizontal lightly doped region, which has a lower impurity concentration than the vertical lightly doped region, is further disposed in an upper side of the vertical lightly doped region. The method comprises forming a gate electrode on a semiconductor substrate of first conductivity type, forming a heavily doped region of second conductivity type in the semiconductor substrate beside the gate electrode, and forming a vertical lightly doped region of second conductivity type surrounding the heavily doped region. The vertical lightly doped region is formed to have a lower impurity concentration and a larger depth than the heavily doped region.
摘要翻译：在用于保护静电放电的半导体器件及其制造方法中，栅电极设置在第一导电类型的半导体衬底上，重掺杂区域和垂直轻掺杂区域围绕重掺杂区域。重掺杂区域和垂直轻掺杂区域具有第二导电类型，并且设置在栅电极两侧的半导体衬底中。垂直轻掺杂区域具有比重掺杂区域更低的杂质浓度和更大的深度。具有比垂直轻掺杂区域低的杂质浓度的水平轻掺杂区域进一步设置在垂直轻掺杂区域的上侧。该方法包括在第一导电类型的半导体衬底上形成栅电极，在栅电极旁边的半导体衬底中形成第二导电类型的重掺杂区，并形成围绕重掺杂区的第二导电类型的垂直轻掺杂区。垂直轻掺杂区域形成为具有比重掺杂区域更低的杂质浓度和更大的深度。

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