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1. 发明授权

US5374575A Method for fabricating MOS transistor 失效
标题翻译：制造MOS晶体管的方法
公开(公告)号：US5374575A
公开(公告)日：1994-12-20
申请号：US156462
申请日：1993-11-23
申请人： Young K. Kim , Kyung S. Kim , Min H. Park
发明人： Young K. Kim , Kyung S. Kim , Min H. Park
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66583 , H01L29/42368 , H01L29/66492 , H01L29/7836 , H01L29/66537
摘要： A method for fabricating an LDD MOS transistor having an improved structure capable of simplifying the fabrication and improving characteristics of the transistor. The methods includes the steps of forming a field oxide film for an active region isolation on a silicon substrate, thickly depositing an oxide film and etching the thick oxide film to form a first opening over an active region, forming side wall spacers in the first opening, implanting p type impurity ions in the silicon substrate through the first opening to form a channel region, filling the first opening with a first polysilicon film, removing the spacers to form second openings respectively in both sides of the first polysilicon film, implanting n type impurity ions in the silicon substrate through the second openings to form low concentration source and drain regions respectively disposed adjacent to both lateral ends of the channel region, removing the first polysilicon film to form a third opening, growing an oxide film over the resulting structure to form a gate oxide film, filling the third opening with a second polysilicon film, patterning the gate oxide film, and implanting n type impurity ions in the silicon substrate to form high concentration source and drain regions respectively disposed adjacent to the low concentration source and drain regions.
摘要翻译：一种制造具有能够简化晶体管的制造和改善特性的改进结构的LDD MOS晶体管的方法。所述方法包括以下步骤：在硅衬底上形成用于有源区隔离的场氧化物膜，厚度沉积氧化膜并蚀刻厚氧化物膜以在有源区上形成第一开口，在第一开口中形成侧壁间隔物通过所述第一开口在所述硅衬底中注入p型杂质离子以形成沟道区，用第一多晶硅膜填充所述第一开口，移除所述间隔物以分别在所述第一多晶硅膜的两侧形成第二开口，将n型通过第二开口在硅衬底中形成杂质离子，以形成分别邻近通道区两个侧端设置的低浓度源极和漏极区域，去除第一多晶硅膜以形成第三个开口，在所得到的结构上生长氧化膜形成栅极氧化膜，用第二多晶硅膜填充第三开口，图案化栅极氧化膜并植入在硅衬底中形成n型杂质离子，以形成分别设置在低浓度源极和漏极区附近的高浓度源极和漏极区域。

2. 发明授权

US5108025A Ceramic-metal composite article and joining method 失效
标题翻译：陶瓷 - 金属复合制品和接合方法
公开(公告)号：US5108025A
公开(公告)日：1992-04-28
申请号：US703079
申请日：1991-05-20
申请人： Shinhoo Kang , John H. Selverian , Hans J. Kim , Edmund M. Dunn , Kyung S. Kim
发明人： Shinhoo Kang , John H. Selverian , Hans J. Kim , Edmund M. Dunn , Kyung S. Kim
IPC分类号： C04B37/02
CPC分类号： C04B37/026 , C04B2237/12 , C04B2237/121 , C04B2237/122 , C04B2237/123 , C04B2237/124 , C04B2237/125 , C04B2237/126 , C04B2237/365 , C04B2237/368 , C04B2237/405 , C04B2237/406 , C04B2237/708 , C04B2237/76 , Y10T403/335 , Y10T403/343 , Y10T403/479 , Y10T403/74
摘要： A ceramic-metal article including a ceramic rod, a metal rod, and a braze joining the ceramic and metal rods at a braze area of a coaxial bore in the metal rod. The bore gradually decreases in diameter, having an inward seat area sized for close sliding fit about the ceramic, a larger brazing area near the joint end, and a void area intermediate the braze and seat areas. The ceramic is seated without brazing in the bore seat area. The side wall between the brazing area and the metal outer surface is about 0.030-0.080 inch. The braze includes an inner braze layer, an outer braze layer, and an interlayer about 0.030-0.090 inch thick. A shoulder between the brazing and void areas supports the interlayer during bonding while preventing bonding between the void area and the ceramic member, leaving a void space between the void area and the ceramic member. A venting orifice extends generally radially through the metal member from the outer surface to the void space. The braze layers are palladium, platinum, gold, silver, copper, nickel, indium, chromium, molybdenum, niobium, iron, aluminum, or alloys thereof. Preferred is a gold-palladium-nickel brazing alloy. The interlayer is nickel, molybdenum, copper, tantalum, tungsten, niobium, aluminum, cobalt, iron, or an alloy thereof.
摘要翻译：一种陶瓷金属制品，包括陶瓷棒，金属棒和钎焊，将金属棒中的同轴孔的钎焊区域处的陶瓷和金属棒接合。孔的直径逐渐减小，具有尺寸适于在陶瓷附近滑动配合的向内座面积，接合端附近的较大的钎焊区域以及钎焊和座位区域之间的空隙区域。陶瓷在没有铜焊的情况下就座在孔座区域。钎焊区域和金属外表面之间的侧壁约为0.030-0.080英寸。钎焊包括内部钎焊层，外部钎焊层和约0.030-0.090英寸厚的中间层。钎焊和空隙区域之间的肩部在接合期间支撑夹层，同时防止空隙区域和陶瓷构件之间的结合，在空隙区域和陶瓷构件之间留下空隙。排气孔从外表面到空隙空间大致径向延伸穿过金属构件。钎焊层是钯，铂，金，银，铜，镍，铟，铬，钼，铌，铁，铝或它们的合金。优选的是金 - 钯 - 镍钎焊合金。中间层是镍，钼，铜，钽，钨，铌，铝，钴，铁或它们的合金。

3. 发明授权

US5497198A Circuit for converting HDTV signals into conventional TV signals with the letter box mode 失效
标题翻译：用信箱模式将HDTV信号转换成传统电视信号的电路
公开(公告)号：US5497198A
公开(公告)日：1996-03-05
申请号：US210175
申请日：1994-03-17
申请人： Kyung S. Kim
发明人： Kyung S. Kim
IPC分类号： H04N5/46 , H04N7/00 , H04N7/01
CPC分类号： H04N7/0122 , H04N7/007 , H04N7/01 , H04N7/0105 , H04N7/0125 , H04N5/46 , Y10S348/913
摘要： A high definition television signal conversion circuit using a side cut mode or a letter box mode. The conversion circuit using the side cut mode comprises an A/D converter for converting a high definition television signal into a digital signal at a first sampling frequency, a line filtering circuit for performing a vertical interpolation of the digital signal from the A/D converter, a line decimation circuit for performing a vertical decimation of output data from the line filtering circuit, a horizontal filtering circuit for performing a horizontal interpolation of output data from the line decimation circuit, a horizontal decimation circuit for performing a horizontal decimation of output data from the horizontal filtering circuit, a memory device for storing output data from the horizontal decimation circuit in response to a write clock and outputting the stored data in response to a read clock, the read clock being determined according to a scanning mode, a D/A converter for converting output data from the memory device into an analog signal at a second sampling frequency, the second sampling frequency being determined according to the scanning mode, and a switch being turned on/off according to the scanning mode to control the data output from the memory device.
摘要翻译：使用侧切模式或信箱模式的高分辨率电视信号转换电路。使用侧切模式的转换电路包括用于将高清晰度电视信号以第一采样频率转换为数字信号的A / D转换器，用于执行来自A / D转换器的数字信号的垂直内插的线路滤波电路，用于对来自线路滤波电路的输出数据进行垂直抽取的行抽选电路，用于对来自线抽取电路的输出数据进行水平插值的水平滤波电路，用于对来自线抽取电路的输出数据进行水平抽取的水平抽取电路，水平滤波电路，用于响应于写时钟存储来自水平抽取电路的输出数据并响应于读时钟输出存储的数据的存储器件，读时钟根据扫描模式确定，D / A 转换器，用于将来自存储器件的输出数据以第二采样频率转换为模拟信号根据扫描模式确定第二采样频率，并且根据扫描模式将开关接通/断开，以控制从存储装置输出的数据。

4. 发明授权

US5193088A High speed ATM cell synchronizing switching apparatus 失效
标题翻译：高速ATM信元同步开关装置
公开(公告)号：US5193088A
公开(公告)日：1993-03-09
申请号：US720005
申请日：1991-06-24
申请人： Jun K. Choi , Mun K. Choi , Kyung S. Kim , Tae S. Jeong , Young S. Shin
发明人： Jun K. Choi , Mun K. Choi , Kyung S. Kim , Tae S. Jeong , Young S. Shin
IPC分类号： H04L12/00 , H04L12/931 , H04L12/933
CPC分类号： H04L12/5601 , H04L49/1576 , H04L2012/5605 , H04L2012/5674 , H04L2012/5678 , H04L2012/5681
摘要： A high speed ATM cell synchronizing switching apparatus is disclosed, and the apparatus includes: a plurality of ATM cell inputting circuits 1 for receiving optical ATM signals; a routing control circuit 2 for receiving address information; a cell gate circuit 3 for transmitting the inputted cells synchronously; a switching information tabling circuit 4 for switching the switching information; and a switching matrix circuit 5 for receiving and outputting the switching control information and the cell data information.
摘要翻译：公开了一种高速ATM信元同步切换装置，该装置包括：多个ATM信元输入电路1，用于接收光ATM信号; 用于接收地址信息的路由控制电路2; 用于同步地发送所输入的单元的单元门电路3; 用于切换切换信息的切换信息提示电路4; 以及用于接收并输出开关控制信息和单元数据信息的开关矩阵电路5。

5. 发明授权

US5552329A Method of making metal oxide semiconductor transistors 失效
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US5552329A
公开(公告)日：1996-09-03
申请号：US472593
申请日：1995-06-06
申请人： Kyung S. Kim , Jun H. Lim
发明人： Kyung S. Kim , Jun H. Lim
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/266 , H01L21/8234
CPC分类号： H01L29/7836 , H01L29/1083 , H01L29/66492 , H01L29/66537 , H01L29/66613 , H01L29/7834
摘要： A method of fabricating a metal oxide semiconductor transistor comprising:a silicon substrate having a first conductivity type in which its central portion having a channel region has a recessed surface and other portion excepting the central portion has a flattened surface, a thin gate oxide film formed on the recessed surface of the silicon substrate, an oxide film formed on the flattened of the silicon substrate and having a thickness a little thicker than that of the gate oxide film, a gate formed on the gate oxide film and having a structure in which its upper surface is flattened and its lower surface is convex, a thick cap oxide film on the gate, a low concentration source region and drain region having a second conductivity type overlapped completely with the gate and formed on a portion adjacent to the channel region of the recessed surface of the silicon substrate, a high concentration source region and drain region having the second conductivity type formed on the flattened surface of the silicon substrate and adjacent to the low concentration of source and drain region; and impurity regions formed on the silicon substrate such that they enclose the low concentration source region and drain region.
摘要翻译：一种制造金属氧化物半导体晶体管的方法，包括：具有第一导电类型的硅衬底，其具有沟道区域的中心部分具有凹陷表面，并且除了中心部分之外的其它部分具有扁平表面，形成薄栅氧化膜在硅衬底的凹入表面上形成氧化膜，该氧化膜形成在硅衬底的平坦化部上，其厚度比栅极氧化膜的厚度稍厚;形成在栅极氧化膜上的栅极，上表面变平且其下表面是凸的，栅极上的厚盖氧化膜，具有第二导电类型的低浓度源区和漏区与栅极完全重叠并形成在与栅极的沟道区相邻的部分上硅衬底的凹面，具有第二导电类型的高浓度源区和漏区形成在扁平面上硅衬底的表面并且与低浓度的源极和漏极区相邻; 以及形成在硅衬底上的杂质区域，使得它们包围低浓度源极区域和漏极区域。

6. 发明授权

US5349235A High density vertically mounted semiconductor package 失效
标题翻译：高密度垂直安装的半导体封装
公开(公告)号：US5349235A
公开(公告)日：1994-09-20
申请号：US111518
申请日：1993-08-25
申请人： Joon K. Lee , Hyeon J. Jeong , Kyung S. Kim , Oh-Sik Kwon
发明人： Joon K. Lee , Hyeon J. Jeong , Kyung S. Kim , Oh-Sik Kwon
IPC分类号： H01L21/56 , H01L23/00 , H01L23/04 , H01L23/28 , H01L23/31 , H01L23/495 , H01L23/50 , H05K1/18 , H05K3/30 , H01L23/16
CPC分类号： H01L23/562 , H01L23/3107 , H01L23/49555 , H05K3/303 , H01L2924/0002 , H05K2201/10454 , H05K2201/10522 , H05K2201/10568 , H05K2201/10696 , Y02P70/613
摘要： A semiconductor chip package comprises leads which protrude from one side of a package body, and support portions which are formed at both ends of the package body on either side of the leads for firmly mounting the package on a printed circuit board (PCB). The support portions are made of a same material as the package body. At the package body, a slot is formed to further protect the leads, and the leads are alternately formed to mount the packages close by. Thus, there is no additional process step for forming holes in the PCB to mount the support portions of the semiconductor package, so the mounting process of the package becomes simpler. The support portions which protrude from the package body permit the package to be mounted on the PCB firmly. The slot and support portions protect the leads and prevent the leads from being deformed by external forces, thereby improving the reliability of the semiconductor package. Also, since the leads are alternately formed and the packages can be mounted near to each other, the package occupies only a small area of the PCB, thereby improving the packing density.
摘要翻译：半导体芯片封装包括从封装主体的一侧突出的引线，以及在引线的两侧形成在封装主体的两端的支撑部分，用于将封装牢固地安装在印刷电路板（PCB）上。支撑部分由与包装体相同的材料制成。在封装主体上，形成一个槽以进一步保护引线，并且引线交替地形成为将封装安装在靠近处。因此，没有用于在PCB中形成孔以安装半导体封装的支撑部分的附加工艺步骤，因此封装的安装过程变得更简单。从包装体突出的支撑部分使得包装件能够牢固地安装在PCB上。槽和支撑部分保护引线并防止引线由于外力而变形，从而提高半导体封装的可靠性。此外，由于引线交替形成并且封装可以彼此靠近地安装，所以封装仅占用PCB的小面积，从而提高封装密度。

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