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    • 10. 发明申请
    • BLACK BOX TIMING MODELING METHOD AND COMPUTER SYSTEM FOR LATCH-BASED SUBSYSTEM
    • 基于LATCH的子系统的黑盒时序建模方法和计算机系统
    • US20080141201A1
    • 2008-06-12
    • US11934252
    • 2007-11-02
    • Kyung Tae DOYoung Hwan KIMHaeng Seon SON
    • Kyung Tae DOYoung Hwan KIMHaeng Seon SON
    • G06F17/50
    • G06F17/5031
    • Provided is a black box timing modeling method for a digital circuit comprising synchronous elements including latches. The method includes: characterizing a setup time arc by extracting a setup time with respect to a rising or falling edge of a clock of a synchronous element with respect to an input connected to the synchronous element and forming the setup time arc using the extracted setup time; and characterizing a clock-to-output delay arc by providing information on an output departure time from an output based on a rising or falling edge of a clock of a closest synchronous element connected to the output, at least partially based on the setup time arc and forming the clock-to-output delay arc. Accordingly, the method can be efficiently used for a latch-based design without re-verifying internal components of the latch-based design during an upper-level verification, thereby reducing verification time and model size.
    • 提供了一种用于数字电路的黑盒定时建模方法,包括具有锁存器的同步元件。 该方法包括:通过相对于连接到同步元件的输入提取相对于同步元件的时钟的上升沿或下降沿的建立时间来表征建立时间弧,并使用所提取的建立时间来形成建立时间弧 ; 以及通过基于建立时间弧至少部分地基于连接到输出的最近同步元件的时钟的上升沿或下降沿从输出提供关于输出离开时间的信息来表征时钟到输出延迟弧 并形成时钟到输出的延迟电弧。 因此,该方法可以有效地用于基于锁存器的设计,而不会在上级验证期间重新验证基于锁存器的设计的内部部件,从而减少验证时间和型号尺寸。