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1. 发明申请

US20120074973A1 ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS 有权
标题翻译：用于在线监测上下文相关效果的模拟参数测试模块
公开(公告)号：US20120074973A1
公开(公告)日：2012-03-29
申请号：US12890146
申请日：2010-09-24
申请人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
发明人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
IPC分类号： G01R31/3187
CPC分类号： G01R31/2831
摘要： An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.
摘要翻译：集成电路（IC）管芯具有管芯上的参数测试模块。半导体衬底具有管芯区域，以及形成在管芯区域的IC部分上的功能IC，包括被配置为执行电路功能的多个电路元件。在与IC部分不同的管芯区域的一部分中，在半导体衬底上形成管芯上参数测试模块。片上参数测试模块包括提供至少一个有源参考MOS晶体管的参考布局，其中有源参考MOS晶体管具有针对多个上下文相关效应参数中的每一个的参考间隔值。在片上参数测试模块上包括多个不同的变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

2. 发明授权

US08669775B2 Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devices 有权
标题翻译：用于在线监测包括MOS器件在内的IC的上下文相关效应的划线测试模块
公开(公告)号：US08669775B2
公开(公告)日：2014-03-11
申请号：US12890123
申请日：2010-09-24
申请人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
发明人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
IPC分类号： G01R31/02
CPC分类号： H01L22/34 , G01R31/2884
摘要： An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.
摘要翻译：一种设备包括具有集成电路（IC）裸片的多个管芯区域，每个管芯具有用于执行电路功能的电路元件，并且在管芯区域之间划线。在划线区域中形成至少一个测试模块。测试模块包括参考布局，该参考布局包括至少一个有源参考MOS晶体管，其具有针对多个上下文相关效应参数中的每一个的参考间隔值和多个变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对多个上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

3. 发明授权

US08664968B2 On-die parametric test modules for in-line monitoring of context dependent effects 有权
标题翻译：片上参数测试模块，用于在线监控上下文相关效应
公开(公告)号：US08664968B2
公开(公告)日：2014-03-04
申请号：US12890146
申请日：2010-09-24
申请人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
发明人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
IPC分类号： G01R31/3187
CPC分类号： G01R31/2831
摘要： An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.
摘要翻译：集成电路（IC）管芯具有管芯上的参数测试模块。半导体衬底具有管芯区域，以及形成在管芯区域的IC部分上的功能IC，包括被配置为执行电路功能的多个电路元件。在与IC部分不同的管芯区域的一部分中，在半导体衬底上形成管芯上参数测试模块。片上参数测试模块包括提供至少一个有源参考MOS晶体管的参考布局，其中有源参考MOS晶体管具有针对多个上下文相关效应参数中的每一个的参考间隔值。在片上参数测试模块上包括多个不同的变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

4. 发明申请

US20120074980A1 SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES 有权
标题翻译：用于在线监测包含MOS器件的IC的上下文相关效果的可选线测试模块
公开(公告)号：US20120074980A1
公开(公告)日：2012-03-29
申请号：US12890123
申请日：2010-09-24
申请人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
发明人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
IPC分类号： G01R31/26 , H01L23/00
CPC分类号： H01L22/34 , G01R31/2884
摘要： An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.
摘要翻译：一种设备包括具有集成电路（IC）裸片的多个管芯区域，每个管芯具有用于执行电路功能的电路元件，并且在管芯区域之间划线。在划线区域中形成至少一个测试模块。测试模块包括参考布局，该参考布局包括至少一个有源参考MOS晶体管，其具有针对多个上下文相关效应参数中的每一个的参考间隔值和多个变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对多个上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

5. 发明申请

US20120078604A1 METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN CMOS PROCESSES THROUGH DESIGN RULE RESTRICTIONS 有权
标题翻译：通过设计规则限制在CMOS工艺中最小化晶体管和模拟分量变化的方法
公开(公告)号：US20120078604A1
公开(公告)日：2012-03-29
申请号：US12889116
申请日：2010-09-23
申请人： Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
发明人： Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.
摘要翻译：各种实施例提供了通过设计规则限制来减少上下文变化的集成电路（IC）设计方法和设计套件。该设计方法可以应用于具有IC设计中的上下文变化的组件（例如，模拟块）。通过在这些组件上绘制覆盖层，可以应用上下文变化减少设计规则限制来减少上下文变化。

6. 发明授权

US08438526B2 Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions 有权
标题翻译：通过设计规则限制最小化CMOS工艺中晶体管和模拟元件变化的方法
公开(公告)号：US08438526B2
公开(公告)日：2013-05-07
申请号：US12889116
申请日：2010-09-23
申请人： Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
发明人： Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.
摘要翻译：各种实施例提供了通过设计规则限制来减少上下文变化的集成电路（IC）设计方法和设计套件。该设计方法可以应用于具有IC设计中的上下文变化的组件（例如，模拟块）。通过在这些组件上绘制覆盖层，可以应用上下文变化减少设计规则限制来减少上下文变化。

7. 发明申请

US20120143569A1 Automated Extraction of Size-Dependent Layout Parameters for Transistor Models 审中-公开
标题翻译：晶体管型号尺寸相关布局参数自动提取
公开(公告)号：US20120143569A1
公开(公告)日：2012-06-07
申请号：US12959830
申请日：2010-12-03
申请人： Oluwamuyiwa Oluwagbemiga Olubuyide , Donald Mark Kolarik
发明人： Oluwamuyiwa Oluwagbemiga Olubuyide , Donald Mark Kolarik
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5036
摘要： A system and method for determining transistor model parameters that account for layout-dependent features in the transistor being modeled, and also in neighboring devices in the same integrated circuit. A computer-readable expression of the integrated circuit layout is retrieved, and active and gate layers in that expression extracted. For a transistor being modeled, its active regions are analyzed to determine whether these regions have a complex shape. Model parameters are derived based on volume effects of the complex shaped active regions. Neighboring active regions that affect parameters of the transistor being modeled are also identified and their effective depth determined. Strain effects due to complex shaped active regions and neighboring elements are thus included in the transistor model.
摘要翻译：用于确定晶体管模型参数的系统和方法，该晶体管模型参数考虑到正在建模的晶体管中与布局相关的特征，以及在同一集成电路中的相邻器件中。检索集成电路布局的计算机可读表达式，并提取该表达式中的活动和门层。对于被建模的晶体管，分析其有源区域以确定这些区域是否具有复杂形状。模型参数是基于复杂形状有源区域的体积效应导出的。还会识别影响正在建模的晶体管参数的相邻有源区，并确定其有效深度。因此，由于复杂形状的有源区和相邻元件引起的应变效应包括在晶体管模型中。

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