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1. 发明申请

US20120078604A1 METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN CMOS PROCESSES THROUGH DESIGN RULE RESTRICTIONS 有权
标题翻译：通过设计规则限制在CMOS工艺中最小化晶体管和模拟分量变化的方法
公开(公告)号：US20120078604A1
公开(公告)日：2012-03-29
申请号：US12889116
申请日：2010-09-23
申请人： Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
发明人： Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.
摘要翻译：各种实施例提供了通过设计规则限制来减少上下文变化的集成电路（IC）设计方法和设计套件。该设计方法可以应用于具有IC设计中的上下文变化的组件（例如，模拟块）。通过在这些组件上绘制覆盖层，可以应用上下文变化减少设计规则限制来减少上下文变化。

2. 发明授权

US08438526B2 Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions 有权
标题翻译：通过设计规则限制最小化CMOS工艺中晶体管和模拟元件变化的方法
公开(公告)号：US08438526B2
公开(公告)日：2013-05-07
申请号：US12889116
申请日：2010-09-23
申请人： Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
发明人： Gregory Charles Baldwin , Younsung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.
摘要翻译：各种实施例提供了通过设计规则限制来减少上下文变化的集成电路（IC）设计方法和设计套件。该设计方法可以应用于具有IC设计中的上下文变化的组件（例如，模拟块）。通过在这些组件上绘制覆盖层，可以应用上下文变化减少设计规则限制来减少上下文变化。

3. 发明申请

US20120074973A1 ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS 有权
标题翻译：用于在线监测上下文相关效果的模拟参数测试模块
公开(公告)号：US20120074973A1
公开(公告)日：2012-03-29
申请号：US12890146
申请日：2010-09-24
申请人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
发明人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
IPC分类号： G01R31/3187
CPC分类号： G01R31/2831
摘要： An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.
摘要翻译：集成电路（IC）管芯具有管芯上的参数测试模块。半导体衬底具有管芯区域，以及形成在管芯区域的IC部分上的功能IC，包括被配置为执行电路功能的多个电路元件。在与IC部分不同的管芯区域的一部分中，在半导体衬底上形成管芯上参数测试模块。片上参数测试模块包括提供至少一个有源参考MOS晶体管的参考布局，其中有源参考MOS晶体管具有针对多个上下文相关效应参数中的每一个的参考间隔值。在片上参数测试模块上包括多个不同的变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

4. 发明授权

US08669775B2 Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devices 有权
标题翻译：用于在线监测包括MOS器件在内的IC的上下文相关效应的划线测试模块
公开(公告)号：US08669775B2
公开(公告)日：2014-03-11
申请号：US12890123
申请日：2010-09-24
申请人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
发明人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
IPC分类号： G01R31/02
CPC分类号： H01L22/34 , G01R31/2884
摘要： An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.
摘要翻译：一种设备包括具有集成电路（IC）裸片的多个管芯区域，每个管芯具有用于执行电路功能的电路元件，并且在管芯区域之间划线。在划线区域中形成至少一个测试模块。测试模块包括参考布局，该参考布局包括至少一个有源参考MOS晶体管，其具有针对多个上下文相关效应参数中的每一个的参考间隔值和多个变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对多个上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

5. 发明授权

US08664968B2 On-die parametric test modules for in-line monitoring of context dependent effects 有权
标题翻译：片上参数测试模块，用于在线监控上下文相关效应
公开(公告)号：US08664968B2
公开(公告)日：2014-03-04
申请号：US12890146
申请日：2010-09-24
申请人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
发明人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
IPC分类号： G01R31/3187
CPC分类号： G01R31/2831
摘要： An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.
摘要翻译：集成电路（IC）管芯具有管芯上的参数测试模块。半导体衬底具有管芯区域，以及形成在管芯区域的IC部分上的功能IC，包括被配置为执行电路功能的多个电路元件。在与IC部分不同的管芯区域的一部分中，在半导体衬底上形成管芯上参数测试模块。片上参数测试模块包括提供至少一个有源参考MOS晶体管的参考布局，其中有源参考MOS晶体管具有针对多个上下文相关效应参数中的每一个的参考间隔值。在片上参数测试模块上包括多个不同的变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

6. 发明申请

US20120074980A1 SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES 有权
标题翻译：用于在线监测包含MOS器件的IC的上下文相关效果的可选线测试模块
公开(公告)号：US20120074980A1
公开(公告)日：2012-03-29
申请号：US12890123
申请日：2010-09-24
申请人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
发明人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
IPC分类号： G01R31/26 , H01L23/00
CPC分类号： H01L22/34 , G01R31/2884
摘要： An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.
摘要翻译：一种设备包括具有集成电路（IC）裸片的多个管芯区域，每个管芯具有用于执行电路功能的电路元件，并且在管芯区域之间划线。在划线区域中形成至少一个测试模块。测试模块包括参考布局，该参考布局包括至少一个有源参考MOS晶体管，其具有针对多个上下文相关效应参数中的每一个的参考间隔值和多个变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对多个上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

7. 发明授权

US08183117B2 Device layout in integrated circuits to reduce stress from embedded silicon-germanium 有权
标题翻译：集成电路中的器件布局，以减少嵌入式硅锗的压力
公开(公告)号：US08183117B2
公开(公告)日：2012-05-22
申请号：US12858586
申请日：2010-08-18
申请人： Gregory Charles Baldwin
发明人： Gregory Charles Baldwin
IPC分类号： H01L21/336
CPC分类号： H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated.
摘要翻译：包括一个或多个晶体管的集成电路，其中源极和漏极区域形成为嵌入的硅 - 锗（eSiGe）。集成电路中的保护环结构形成在单晶硅中，而不是在eSiGe中。在一个示例中，p沟道MOS晶体管具有以eSiGe形成的源极/漏极区域，而形成p型保护环的位置被从凹陷蚀刻和eSiGe选择性外延掩模。消除了在保护环和类似结构的角落处的浓缩晶体应变引起的缺陷。

8. 发明申请

US20120280324A1 SRAM STRUCTURE AND PROCESS WITH IMPROVED STABILITY 审中-公开
标题翻译：具有改进稳定性的SRAM结构和过程
公开(公告)号：US20120280324A1
公开(公告)日：2012-11-08
申请号：US13287737
申请日：2011-11-02
申请人： Weize Xiong , Gregory Charles Baldwin
发明人： Weize Xiong , Gregory Charles Baldwin
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/1104 , H01L21/823807 , H01L21/823814
摘要： An SRAM memory cell with reduced SiGe formation area using a gate extension (530) that extends over the STI/p-active interface (536). A process for forming an SRAM memory cell with reduced SiGe formation area. A process for forming an SRAM memory cell with improved read/write stability.
摘要翻译：使用在STI / p有源接口（536）上延伸的栅极延伸（530），SiGe形成区域减小的SRAM存储单元。用于形成具有降低的SiGe形成面积的SRAM存储单元的工艺。一种用于形成具有改善的读/写稳定性的SRAM存储单元的工艺。

9. 发明授权

US08748256B2 Integrated circuit having silicide block resistor 有权
标题翻译：具有硅化物阻抗电阻的集成电路
公开(公告)号：US08748256B2
公开(公告)日：2014-06-10
申请号：US13366903
申请日：2012-02-06
申请人： Song Zhao , Gregory Charles Baldwin , Shashank S. Ekbote , Youn Sung Choi
发明人： Song Zhao , Gregory Charles Baldwin , Shashank S. Ekbote , Youn Sung Choi
IPC分类号： H01L27/088
CPC分类号： H01L27/0629
摘要： A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.
摘要翻译：一种形成包括硅化物阻挡多晶硅电阻（SIBLK聚电阻）的集成电路（IC）的方法包括在衬底的顶部半导体表面中形成介电隔离区。形成多晶硅层，其包括在电介质隔离区域上的图案化电阻多晶硅和顶部半导体表面上的栅极多晶硅。使用第一共享金属氧化物半导体（MOS）/电阻器多晶硅注入电平进行植入，以同时用至少第一掺杂剂注入MOS图案化的多晶硅和栅极多晶硅。然后使用第二共享MOS /电阻器多晶硅注入电平进行植入，以同时用至少第二掺杂剂注入MOS图案化电阻器多晶硅，栅极多晶硅以及MOS晶体管的源极和漏极区域。金属硅化物形成在图案化电阻器多晶硅的顶表面的第一和第二部分上以形成SIBLK多晶硅电阻器。

10. 发明授权

US08791527B2 Device layout in integrated circuits to reduce stress from embedded silicon—germanium 有权
标题翻译：集成电路中的器件布局，以减少嵌入式硅锗的压力
公开(公告)号：US08791527B2
公开(公告)日：2014-07-29
申请号：US13453590
申请日：2012-04-23
申请人： Gregory Charles Baldwin
发明人： Gregory Charles Baldwin
IPC分类号： H01L27/088 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated.
摘要翻译：包括一个或多个晶体管的集成电路，其中源极和漏极区域形成为嵌入的硅 - 锗（eSiGe）。集成电路中的保护环结构形成在单晶硅中，而不是在eSiGe中。在一个示例中，p沟道MOS晶体管具有以eSiGe形成的源极/漏极区域，而形成p型保护环的位置被从凹陷蚀刻和eSiGe选择性外延掩模。消除了在保护环和类似结构的角落处的浓缩晶体应变引起的缺陷。

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