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1. 发明申请

US20120119301A1 METHOD FOR IMPROVING DEVICE PERFORMANCE USING DUAL STRESS LINER BOUNDARY 有权
标题翻译：使用双应力衬里边界改进设备性能的方法
公开(公告)号：US20120119301A1
公开(公告)日：2012-05-17
申请号：US13288664
申请日：2011-11-03
申请人： Youn Sung Choi , Greg Charles Baldwin
发明人： Youn Sung Choi , Greg Charles Baldwin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0207 , H01L21/823807 , H01L27/0203 , H01L27/092 , H01L27/0925 , H01L29/0638 , H01L29/1033 , H01L29/7843
摘要： An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.
摘要翻译：一个集成电路，其DSL边界垂直于晶体管门，主要在nwell内部，并且DSL边界平行于晶体管门主要在nwell外面。一种用于形成集成电路的方法，该集成电路具有垂直于晶体管门的DSL边界，主要在nwell内部，并且DSL边界平行于晶体管门主要在nwell外部。

2. 发明授权

US08859357B2 Method for improving device performance using dual stress liner boundary 有权
标题翻译：使用双应力衬垫边界提高器件性能的方法
公开(公告)号：US08859357B2
公开(公告)日：2014-10-14
申请号：US13288664
申请日：2011-11-03
申请人： Youn Sung Choi , Greg Charles Baldwin
发明人： Youn Sung Choi , Greg Charles Baldwin
IPC分类号： H01L21/00 , H01L21/8238 , H01L27/02 , H01L29/78
CPC分类号： H01L27/0207 , H01L21/823807 , H01L27/0203 , H01L27/092 , H01L27/0925 , H01L29/0638 , H01L29/1033 , H01L29/7843
摘要： An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.
摘要翻译：一个集成电路，其DSL边界垂直于晶体管门，主要在nwell内部，并且DSL边界平行于晶体管门主要在nwell外面。一种用于形成集成电路的方法，该集成电路具有垂直于晶体管门的DSL边界，主要在nwell内部，并且DSL边界平行于晶体管门主要在nwell外部。

3. 发明授权

US08664968B2 On-die parametric test modules for in-line monitoring of context dependent effects 有权
标题翻译：片上参数测试模块，用于在线监控上下文相关效应
公开(公告)号：US08664968B2
公开(公告)日：2014-03-04
申请号：US12890146
申请日：2010-09-24
申请人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
发明人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
IPC分类号： G01R31/3187
CPC分类号： G01R31/2831
摘要： An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.
摘要翻译：集成电路（IC）管芯具有管芯上的参数测试模块。半导体衬底具有管芯区域，以及形成在管芯区域的IC部分上的功能IC，包括被配置为执行电路功能的多个电路元件。在与IC部分不同的管芯区域的一部分中，在半导体衬底上形成管芯上参数测试模块。片上参数测试模块包括提供至少一个有源参考MOS晶体管的参考布局，其中有源参考MOS晶体管具有针对多个上下文相关效应参数中的每一个的参考间隔值。在片上参数测试模块上包括多个不同的变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

4. 发明申请

US20120074980A1 SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES 有权
标题翻译：用于在线监测包含MOS器件的IC的上下文相关效果的可选线测试模块
公开(公告)号：US20120074980A1
公开(公告)日：2012-03-29
申请号：US12890123
申请日：2010-09-24
申请人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
发明人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
IPC分类号： G01R31/26 , H01L23/00
CPC分类号： H01L22/34 , G01R31/2884
摘要： An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.
摘要翻译：一种设备包括具有集成电路（IC）裸片的多个管芯区域，每个管芯具有用于执行电路功能的电路元件，并且在管芯区域之间划线。在划线区域中形成至少一个测试模块。测试模块包括参考布局，该参考布局包括至少一个有源参考MOS晶体管，其具有针对多个上下文相关效应参数中的每一个的参考间隔值和多个变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对多个上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

5. 发明授权

US08748256B2 Integrated circuit having silicide block resistor 有权
标题翻译：具有硅化物阻抗电阻的集成电路
公开(公告)号：US08748256B2
公开(公告)日：2014-06-10
申请号：US13366903
申请日：2012-02-06
申请人： Song Zhao , Gregory Charles Baldwin , Shashank S. Ekbote , Youn Sung Choi
发明人： Song Zhao , Gregory Charles Baldwin , Shashank S. Ekbote , Youn Sung Choi
IPC分类号： H01L27/088
CPC分类号： H01L27/0629
摘要： A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.
摘要翻译：一种形成包括硅化物阻挡多晶硅电阻（SIBLK聚电阻）的集成电路（IC）的方法包括在衬底的顶部半导体表面中形成介电隔离区。形成多晶硅层，其包括在电介质隔离区域上的图案化电阻多晶硅和顶部半导体表面上的栅极多晶硅。使用第一共享金属氧化物半导体（MOS）/电阻器多晶硅注入电平进行植入，以同时用至少第一掺杂剂注入MOS图案化的多晶硅和栅极多晶硅。然后使用第二共享MOS /电阻器多晶硅注入电平进行植入，以同时用至少第二掺杂剂注入MOS图案化电阻器多晶硅，栅极多晶硅以及MOS晶体管的源极和漏极区域。金属硅化物形成在图案化电阻器多晶硅的顶表面的第一和第二部分上以形成SIBLK多晶硅电阻器。

6. 发明申请

US20140054710A1 Reduction of Proximity Effects in Field-Effect Transistors with Embedded Silicon-Germanium Source and Drain Regions 审中-公开
标题翻译：减少具有嵌入式硅锗源和漏极区域的场效应晶体管的接近效应
公开(公告)号：US20140054710A1
公开(公告)日：2014-02-27
申请号：US13591976
申请日：2012-08-22
申请人： Youn Sung Choi , Deborah Riley , Shashank Sureshchandra Ekbote
发明人： Youn Sung Choi , Deborah Riley , Shashank Sureshchandra Ekbote
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit and method of fabricating the same utilizing embedded silicon-germanium (SiGe) source/drain regions, and in which the proximity effect of nearby shallow trench isolation structures is reduced. Embedded SiGe source/drain structures are formed by selective epitaxy into recesses etched into the semiconductor surface, on either side of each gate electrode. The SiGe structures overfill the recesses by at least about 30% of the depth of the recesses, as measured from the interface between the channel region and the overlying gate dielectric at the edge of the gate electrode. This overfill has been observed to reduce proximity effects of nearby shallow trench isolation structures on nearby transistors. Additional reduction in the proximity effect can be obtained by ensuring sufficient spacing between the edge of the gate electrode and a parallel edge of the nearest shallow trench isolation structure.
摘要翻译：一种集成电路及其制造方法，利用嵌入的硅 - 锗（SiGe）源极/漏极区域，其中附近的浅沟槽隔离结构的邻近效应降低。嵌入式SiGe源极/漏极结构通过选择性外延形成蚀刻到半导体表面中的每个栅电极的任一侧上的凹槽。 SiGe结构从沟槽区域和栅电极边缘处的上覆栅极电介质之间的界面测量到，凹槽的深度至少大约为凹槽深度的30％。已经观察到这种过度填充以减少附近的晶体管附近的浅沟槽隔离结构的邻近效应。可以通过确保栅电极的边缘与最近的浅沟槽隔离结构的平行边缘之间的足够间隔来获得邻近效应的附加减小。

7. 发明申请

US20120074973A1 ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS 有权
标题翻译：用于在线监测上下文相关效果的模拟参数测试模块
公开(公告)号：US20120074973A1
公开(公告)日：2012-03-29
申请号：US12890146
申请日：2010-09-24
申请人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
发明人： Gregory Charles Baldwin , Thomas J. Aton , Kayvan Sadra , Oluwamuyiwa Oluwagbemiga Olubuyide , Youn Sung Choi
IPC分类号： G01R31/3187
CPC分类号： G01R31/2831
摘要： An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.
摘要翻译：集成电路（IC）管芯具有管芯上的参数测试模块。半导体衬底具有管芯区域，以及形成在管芯区域的IC部分上的功能IC，包括被配置为执行电路功能的多个电路元件。在与IC部分不同的管芯区域的一部分中，在半导体衬底上形成管芯上参数测试模块。片上参数测试模块包括提供至少一个有源参考MOS晶体管的参考布局，其中有源参考MOS晶体管具有针对多个上下文相关效应参数中的每一个的参考间隔值。在片上参数测试模块上包括多个不同的变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

8. 发明授权

US08669775B2 Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devices 有权
标题翻译：用于在线监测包括MOS器件在内的IC的上下文相关效应的划线测试模块
公开(公告)号：US08669775B2
公开(公告)日：2014-03-11
申请号：US12890123
申请日：2010-09-24
申请人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
发明人： Youn Sung Choi , Oluwamuyiwa Oluwagbemiga Olubuyide , Gregory Charles Baldwin
IPC分类号： G01R31/02
CPC分类号： H01L22/34 , G01R31/2884
摘要： An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.
摘要翻译：一种设备包括具有集成电路（IC）裸片的多个管芯区域，每个管芯具有用于执行电路功能的电路元件，并且在管芯区域之间划线。在划线区域中形成至少一个测试模块。测试模块包括参考布局，该参考布局包括至少一个有源参考MOS晶体管，其具有针对多个上下文相关效应参数中的每一个的参考间隔值和多个变体布局。每个变体布局提供至少一个有源变体MOS晶体管，其针对多个上下文相关效应参数中的至少一个提供关于参考间隔值的变化。

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