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    • 2. 发明申请
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US20080151676A1
    • 2008-06-26
    • US12000629
    • 2007-12-14
    • Yosuke Mizutani
    • Yosuke Mizutani
    • G11C5/14
    • G11C5/143H01L2224/48091H01L2224/4813H01L2924/13091H01L2924/00014H01L2924/00
    • A semiconductor integrated circuit in which a semiconductor chip 4 having a semiconductor memory and a mother chip 2 having logic circuit are mounted in a single package, wherein the leak current of the semiconductor chip 4 is reduced in standby state. A switch cell 20 that connects to the power pad 10 of the semiconductor chip 4 and that supplies power voltage from the exterior to the semiconductor chip 4 is provided to the mother chip 2. The switch cell 20 cuts off the connection between the power pad 10 of the semiconductor chip 4 and the power voltage line of the semiconductor memory of the mother chip 2 by using a control signal from a control circuit when the semiconductor memory is in standby mode. Leak current generated in the semiconductor memory can thereby be reduced.
    • 具有半导体存储器的半导体芯片4和具有逻辑电路的母芯片2的半导体集成电路安装在单个封装中,其中半导体芯片4的漏电流在待机状态下降低。 连接到半导体芯片4的功率垫10并且从外部向半导体芯片4提供电源电压的开关单元20被提供给母芯片2。 当半导体存储器处于待机模式时,开关单元20通过使用来自控制电路的控制信号来切断半导体芯片4的电源焊盘10与母芯片2的半导体存储器的电源电压线之间的连接。 因此可以减少在半导体存储器中产生的泄漏电流。
    • 3. 发明授权
    • Video signal converter
    • 视频信号转换器
    • US5677738A
    • 1997-10-14
    • US757902
    • 1996-11-27
    • Yosuke MizutaniSeiya Ota
    • Yosuke MizutaniSeiya Ota
    • H04N7/01
    • H04N7/0105
    • A video signal converter comprising a frequency setting circuit, a first clock generator, a second clock generator, an analog-to-digital converter, a line conversion ratio setting circuit, a number of scanning lines converter, a frame memory, a writing controller, a reading controller and a digital-to-analog converter is disclosed. The frequency setting circuit sets a first frequency Fi which satisfies a formula: Fi.ltoreq.(To.times.Fo)/Ti, where Ti is a horizontal scanning period of a first analog video signal, To is a horizontal scanning period of a second analog video signal and Fo is a second frequency. The line conversion ratio setting circuit sets a line conversion ratio R which satisfies an equation: R=m/k, based on a width-to-height ratio 1/m of each pixel of the first digital video data and a width-to-height ratio 1/k of each pixel of second digital video data. The number of scanning lines converter converts any digital video data having a first number of scanning lines to varied digital video data having a second number of scanning lines, the second number of scanning lines being R-times the first number of scanning lines. The writing controller memorizes the first digital video data into the memory in synchronization with the first clock of the first frequency Fi. The reading controller reads the first digital video data from the memory in synchronization with the second clock of the second frequency Fo to generate the second digital video data.
    • 一种视频信号转换器,包括频率设置电路,第一时钟发生器,第二时钟发生器,模数转换器,线路转换比率设置电路,多个扫描线转换器,帧存储器,写入控制器, 公开了一种读取控制器和一个数模转换器。 频率设定电路设定第一频率Fi,其满足以下公式:Fi