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2. 发明授权

US5317530A Rounding operation circuit 失效
标题翻译：四舍五入运算电路
公开(公告)号：US5317530A
公开(公告)日：1994-05-31
申请号：US34108
申请日：1993-03-22
申请人： Yoshitaka Toriumi
发明人： Yoshitaka Toriumi
IPC分类号： G06F7/38 , G06F7/48
CPC分类号： G06F7/48 , G06F7/49963
摘要： A rounding operation circuit for arithmetic logic unit of a signal processor provided for counting fractions over 1/2 as one and disregarding the rest for the positive and negative number, which comprises a decoder circuit having an (n+1)-long input to which a first input signal represented by two's complement and a second n-bit long input signal for specifying the rounded position of the first signal are entered, when the first input signal is positive, a signal in which the bit at the rounded position is "1" and the rest is "0" is emitted based on the second input signal and, when the first input signal is negative, a signal in which the bits less significant than the bit at the rounded position are all "1" and the rest is "0" is emitted; arithmetic logic unit for adding the output signal of this decoder circuit and the first input signal; and a rounding circuit for counting 1 and cutting away 0 positively and negatively symmetrically to any rounding position, to allow a fast and accurate rounding operation.
摘要翻译：一种信号处理器的算术逻辑单元的舍入运算电路，用于将1/2以上的分数计数为1，忽略正数和负数的余数，其包括具有（n + 1）长输入的解码器电路，输入由二进制补码表示的第一输入信号和用于指定第一信号的四舍五入位置的第二n位长输入信号，当第一输入信号为正时，在四舍五入位置的位为“1”的信号 “，其余的”0“是基于第二输入信号发射的，当第一输入信号为负时，其中比在倒圆位置处的比特小的比特全部为”1“的信号，其余的是发出“0” 用于将该解码器电路的输出信号和第一输入信号相加的算术逻辑单元; 以及用于对1进行计数的圆形回路，并将0与任何舍入位置正对称地切除，以允许快速且精确的舍入操作。

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