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1. 发明授权

US06289469B1 Semiconductor integrated circuit having a plurality of processing circuits respectively executing necessary processes and a plurality of data holding circuits corresponding to the processing circuits 失效
标题翻译：具有分别执行必要处理的多个处理电路的半导体集成电路和与处理电路对应的多个数据保持电路
公开(公告)号：US06289469B1
公开(公告)日：2001-09-11
申请号：US09139328
申请日：1998-08-25
申请人： Yoshio Sakata , Yoshio Tokuno , Junichi Tamura , Yumiko Uehara
发明人： Yoshio Sakata , Yoshio Tokuno , Junichi Tamura , Yumiko Uehara
IPC分类号： G06F104
CPC分类号： G01R31/318536
摘要： A control signal generating circuit for generating control signals, based on a first clock signal, a second clock signal and a mode setting signal, and a plurality of scanpath circuits. Operation of each of the scanpath circuits is controlled according to the generated control signals. The control signal generating circuit and scanpath circuits are provided in a semiconductor integrated circuit having reduced size.
摘要翻译：一种控制信号发生电路，用于基于第一时钟信号，第二时钟信号和模式设置信号以及多个扫描路径电路产生控制信号。根据生成的控制信号来控制各扫描路径电路的动作。控制信号发生电路和扫描路径电路设置在尺寸减小的半导体集成电路中。

2. 发明授权

US5216628A Absolute value arithmetic circuit 失效
标题翻译：绝对值算术电路
公开(公告)号：US5216628A
公开(公告)日：1993-06-01
申请号：US732818
申请日：1991-07-19
申请人： Hideo Mizutani , Noritsugu Matsubishi , Yoshio Tokuno
发明人： Hideo Mizutani , Noritsugu Matsubishi , Yoshio Tokuno
IPC分类号： G06F7/50 , G06F7/544
CPC分类号： G06F7/544 , G06F2207/5442
摘要： An absolute value arithmetic circuit for computing the absolute value of two binary input signals, includes: a computing circuit for obtaining a difference between the two input signals, a 1's complementor for non-inverting or inverting an output from the computing circuit in accordance with a positive sign bit or a negative sign bit of the output, a priority encoder for searching an output from the 1's complementor for the position of a first "0" bit from the least significant digit of the output and delivering an encoder output indicating the position of the first "0" bit, and a bit inverting circuit for inverting and delivering a bit row from the least significant digit bit to the "0" bit in the output from the 1's complementor in accordance with the encoder output, and directly delivering a bit row from a bit higher than the "0" bit to the most significant digit bit of the output without inverting them.
摘要翻译：用于计算两个二进制输入信号的绝对值的绝对值运算电路包括：用于获得两个输入信号之间的差的计算电路，用于根据计算电路的非反相或反相运算电路的输出的1的补码输出的正号位或负号位，用于从输出的最低有效位搜索来自1的补码器的输出的第一“0”位的位置的优先编码器，并且传送指示位置的编码器输出第一个“0”位，以及一个位反相电路，用于根据编码器输出从1的补码器的输出中将位行从最低有效数位位反转和传送到“0”位，并直接传送位从高于“0”位到输出的最高有效位，而不反转它们。

3. 发明申请

US20070229124A1 Driving circuit 有权
标题翻译：驱动电路
公开(公告)号：US20070229124A1
公开(公告)日：2007-10-04
申请号：US11700835
申请日：2007-02-01
申请人： Yoshio Tokuno
发明人： Yoshio Tokuno
IPC分类号： H03B1/00
CPC分类号： H03K5/1534 , H03K17/04106 , H03K17/122 , H03K17/145 , H03K17/162 , H03K17/6872 , H03K19/00384 , H03K19/01707
摘要： In addition to two-stage CMOS inverters for inverting and amplifying the input signal IN, a rising edge detector 3 for detecting the rising edge of the input signal IN, and outputting a rising edge detection signal S3 having a pulse width corresponding to the ambient temperature, and a PMOS 5 for driving the output node NO to the power supply potential VDD according to the rising edge detection signal S3, and the falling edge detector 4 for detecting the falling edge of the input signal IN and outputting a falling edge detection signal S4 having a pulse width corresponding to the ambient temperature, and an NMOS 6 driving the output node NO to the ground potential GND according to the falling edge detection signal S4. When the ambient temperature rises, and the delay time of the CMOS inverters 1, 2 are thereby increased, the pulse widths of the rising edge detection signal S3, and the falling edge detection signal S4 are also increased, and because of the additional driving by means of the PMOS 5 and the NMOS 6, the delay time is reduced. Thus, the variation in the delay time in the driving circuit in an LSI, due to the ambient temperature change can be restrained.
摘要翻译：除了用于反相和放大输入信号IN的两级CMOS反相器之外，还提供用于检测输入信号IN的上升沿的上升沿检测器3，并且输出具有对应于环境的脉冲宽度的上升沿检测信号S 3 温度和用于根据上升沿检测信号S 3将输出节点NO驱动到电源电位VDD的PMOS5，以及用于检测输入信号IN的下降沿的下降沿检测器4，并输出下降沿检测具有对应于环境温度的脉冲宽度的信号S 4和根据下降沿检测信号S4将输出节点NO驱动到地电位GND的NMOS 6。当环境温度升高，并且CMOS反相器1,2的延迟时间因此增加时，上升沿检测信号S 3和下降沿检测信号S4的脉冲宽度也增加，并且由于额外的通过PMOS 5和NMOS 6驱动，延迟时间减少。因此，可以抑制由于环境温度变化引起的LSI中的驱动电路中的延迟时间的变化。

4. 发明授权

US07508242B2 Driving circuit that eliminates effects of ambient temperature variations and increases driving capacity 有权
标题翻译：驱动电路，消除环境温度变化的影响并增加驱动能力
公开(公告)号：US07508242B2
公开(公告)日：2009-03-24
申请号：US11700835
申请日：2007-02-01
申请人： Yoshio Tokuno
发明人： Yoshio Tokuno
IPC分类号： H03K3/00
CPC分类号： H03K5/1534 , H03K17/04106 , H03K17/122 , H03K17/145 , H03K17/162 , H03K17/6872 , H03K19/00384 , H03K19/01707
摘要： In addition to two-stage CMOS inverters inverting and amplifying the input signal, a rising edge detector detects the rising edge of the input signal, and outputs a rising edge detection signal having a pulse width corresponding to ambient temperature, a PMOS drives the output node to the power supply potential according to the rising edge detection signal, a falling edge detector detects the falling edge of the input signal and outputs a falling edge detection signal having a pulse width corresponding to ambient temperature, and an NMOS drives the output node to ground potential according to the falling edge detection signal. When ambient temperature rises, and delay time of the inverters are thereby increased, pulse widths of the rising and falling edge detection signals are increased. The additional driving restrains delay time variation in a driving circuit due to ambient temperature change.
摘要翻译：除了反相和放大输入信号的两级CMOS反相器之外，上升沿检测器检测输入信号的上升沿，并输出具有与环境温度相对应的脉冲宽度的上升沿检测信号，PMOS驱动输出节点根据上升沿检测信号进入电源电位，下降沿检测器检测输入信号的下降沿，并输出具有对应于环境温度的脉冲宽度的下降沿检测信号，NMOS将输出节点驱动到地根据下降沿检测信号的电位。当环境温度上升时，逆变器的延迟时间由此增加，上升沿和下降沿检测信号的脉冲宽度增加。附加驱动限制了由于环境温度变化引起的驱动电路中的延迟时间变化。

5. 发明授权

US5235536A Absolute difference processor element processing unit, and processor 失效
标题翻译：绝对差异处理器元件处理单元和处理器
公开(公告)号：US5235536A
公开(公告)日：1993-08-10
申请号：US762348
申请日：1991-09-19
申请人： Noritsugu Matsubishi , Yoshio Tokuno , Hiroshi Masaki , Masato Yamazaki
发明人： Noritsugu Matsubishi , Yoshio Tokuno , Hiroshi Masaki , Masato Yamazaki
IPC分类号： G06F7/505 , G06F7/53 , G06F7/533 , G06F7/544 , G06F7/57 , G06F15/80 , G06F17/16
CPC分类号： G06F7/57 , G06F17/16 , G06F7/544 , G06F7/5443 , G06F2207/5442
摘要： A processing unit for executing parallel cumulative absolute difference operations in a first mode, and an inner product operation in a second mode, includes an input bus group for receiving first input data, second input data, and third input data. A plurality of processor elements are coupled to the input bus group, each processor element being coupled to compute a cumulative absolute difference between the first input data and the second input data in the first mode, and to compute and accumulate one term of Booth's algorithm for multiplying the first input data by the third input data in the second mode. An output bus group is coupled to the processor elements, for receiving the terms of Booth's algorithm. An accumulator circuit is coupled to the output bus group, for shifting and adding terms of Booth's algorithm output by the processor elements.

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