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1. 发明授权

US5407870A Process for fabricating a semiconductor device having a high reliability dielectric material 失效
标题翻译：制造具有高可靠性电介质材料的半导体器件的工艺
公开(公告)号：US5407870A
公开(公告)日：1995-04-18
申请号：US71885
申请日：1993-06-07
申请人： Yoshio Okada , Philip J. Tobin
发明人： Yoshio Okada , Philip J. Tobin
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L21/285
CPC分类号： H01L21/28273 , H01L21/28167 , H01L21/28176 , H01L29/511 , H01L29/66825
摘要： A process for fabricating a high-reliability composite dielectric layer (19) includes the formation of a first oxynitride layer (14) on the surface (12) of a silicon substrate (10). The formation of the first oxynitride layer (14) is followed by an oxidation step to form a silicon dioxide layer (16) at the surface (12) of the substrate (10) and underlying the first oxynitride layer (14). The composite dielectric layer (19) is completed by exposing the substrate (10) to nitrous oxide, and diffusing a nitrogen bearing species through both the silicon dioxide layer (16) and the first oxynitride layer (14) to form a second oxynitride layer (18) underlying the silicon dioxide layer (16). The composite dielectric layer (19) exhibits a nitrogen-rich region at the interface between second oxynitride layer (18) and the silicon substrate (10). A second nitrogen rich region is also formed near the surface of the first oxynitride layer (14).
摘要翻译：制造高可靠性复合电介质层（19）的工艺包括在硅衬底（10）的表面（12）上形成第一氮氧化物层（14）。第一氮氧化物层（14）的形成之后是氧化步骤，以在衬底（10）的表面（12）处形成二氧化硅层（16），并且位于第一氮氧化物层（14）下方。通过将基板（10）暴露于一氧化二氮并通过二氧化硅层（16）和第一氮氧化物层（14）两者扩散含氮物质来形成复合介电层（19），以形成第二氮氧化物层 18）位于二氧化硅层（16）下面。复合电介质层（19）在第二氧氮化物层（18）和硅衬底（10）之间的界面处显示富氮区域。在第一氮氧化物层（14）的表面附近还形成有第二富氮区域。

2. 发明授权

US07091568B2 Electronic device including dielectric layer, and a process for forming the electronic device 有权
标题翻译：包括电介质层的电子器件，以及用于形成电子器件的工艺
公开(公告)号：US07091568B2
公开(公告)日：2006-08-15
申请号：US11023014
申请日：2004-12-22
申请人： Rama I. Hegde , Alexander A. Demkov , Philip J. Tobin , Dina H. Triyoso
发明人： Rama I. Hegde , Alexander A. Demkov , Philip J. Tobin , Dina H. Triyoso
IPC分类号： H01L29/76 , H01L21/8242
CPC分类号： H01L29/517 , C23C16/45529 , C23C16/45531 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/28185 , H01L21/28194 , H01L21/28229 , H01L21/3141 , H01L21/31641 , H01L21/31645 , H01L21/823842 , H01L29/4966
摘要： A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO2)(1-x)(ZrO2)x, wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.
摘要翻译：材料的混合物可以在电子器件的层内使用，以改善该层的电学和物理性质。在一组实施例中，该层可以是介电层，例如栅极介电层或电容器电介质层。电介质层可以包括O和两个或多个不同的金属元素。在一个具体实施方式中，两个不同的元件可以具有相同的单一氧化状态并且彼此可混溶。在一个实施例中，电介质层可以包括（HfO 2 2）（1-x）（ZrO 2 2）x 其中x在0和1之间.Hf和Zr中的每一个具有+4的单一氧化态。其他组合是可能的。改善的电学和物理性质可以包括更好地控制晶粒尺寸，晶粒尺寸分布，跨越衬底的层的厚度，改进的载流子迁移率，阈值电压稳定性或其任何组合。

3. 发明授权

US06972224B2 Method for fabricating dual-metal gate device 有权
公开(公告)号：US06972224B2
公开(公告)日：2005-12-06
申请号：US10400896
申请日：2003-03-27
申请人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
发明人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

4. 发明授权

US5712208A Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants 失效
标题翻译：形成具有多个掺入的原子掺杂剂的半导体复合栅极电介质的方法
公开(公告)号：US5712208A
公开(公告)日：1998-01-27
申请号：US449964
申请日：1995-05-25
申请人： Hsing-Huang Tseng , Philip J. Tobin , Keith E. Witek
发明人： Hsing-Huang Tseng , Philip J. Tobin , Keith E. Witek
IPC分类号： H01L21/28 , H01L21/336 , H01L29/08 , H01L29/51 , H01L21/225 , H01L21/3115
CPC分类号： H01L29/513 , H01L21/28035 , H01L21/28176 , H01L21/28238 , H01L21/28273 , H01L29/0847 , H01L29/518 , H01L29/66575 , H01L21/28194 , H01L21/28202 , H01L21/28211 , Y10S438/923
摘要： A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of both nitrogen and fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features which the nitrogen/fluorine interface further improves the dielectric's features.
摘要翻译：通过提供具有表面的基底层（12）形成半导体电介质（10）。在基层（12）的表面形成有薄界面层（13）。薄界面层具有氮和氟的显着浓度。在界面层（13）上形成热氧化层（14）。沉积的介电层（16）形成在热氧化物层（14）上。沉积的介电层（16）任选地通过热热循环致密化。沉积的介电层（16）具有与热氧化物层（14）中的微孔不对准的微孔，以提供增强的特征，氮/氟界面进一步改善电介质的特征。

5. 发明授权

US5580815A Process for forming field isolation and a structure over a semiconductor substrate 失效
标题翻译：用于形成场隔离的工艺和半导体衬底上的结构
公开(公告)号：US5580815A
公开(公告)日：1996-12-03
申请号：US200029
申请日：1994-02-22
申请人： Ting C. Hsu , Laureen H. Parker , David G. Kolar , Philip J. Tobin , Hsing-Huang Tseng , Lisa K. Garling , Vida Ilderem
发明人： Ting C. Hsu , Laureen H. Parker , David G. Kolar , Philip J. Tobin , Hsing-Huang Tseng , Lisa K. Garling , Vida Ilderem
IPC分类号： H01L21/32 , H01L21/76
CPC分类号： H01L21/32
摘要： An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.
摘要翻译：在LOCOS场隔离工艺中使用时，形成退火的非晶硅层，形成场隔离区。退火的非晶硅层有助于减少与常规LOCOS场隔离过程相比的侵蚀，并且有助于降低与PBL场隔离工艺相比在衬底内形成凹坑的可能性。退火的非晶硅层可以用于形成场隔离区域，其限定包括MOSFET和双极晶体管的晶体管之间的有源区。可以使用掺杂硅或富硅的氮化硅层代替常规材料。如果在不高于600摄氏度的温度下沉积氮化硅层，则可以在形成氮化硅层之后执行非晶硅层的退火。

6. 发明授权

US5208189A Process for plugging defects in a dielectric layer of a semiconductor device 失效
标题翻译：在半导体器件的电介质层中插入缺陷的工艺
公开(公告)号：US5208189A
公开(公告)日：1993-05-04
申请号：US769049
申请日：1991-09-30
申请人： Bich-Yen Nguyen , Philip J. Tobin
发明人： Bich-Yen Nguyen , Philip J. Tobin
IPC分类号： H01L21/318 , H01L21/28 , H01L21/3105 , H01L21/314 , H01L29/51
CPC分类号： H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L29/518 , Y10S148/025 , Y10S148/043 , Y10S148/081 , Y10S148/118
摘要： Defects in a thin dielectric layer of a semiconductor device are plugged by a discontinuous layer to maintain integrity of the dielectric without degrading the reliability of the device. In one form of the invention, a semiconductor device (10) includes an oxide layer (14) formed on a substrate material (12). Growth of a nitride layer (18), using CVD techniques, is initiated in any defects (16) in the oxide layer, but growth is terminated prior to entering a continuous growth stage. By plugging the defects with nitride without forming a continuous nitride layer, defect density in thin oxides is reduced without experiencing disadvantages associated with thick oxide-nitride stacks. The invention is also applicable to plugging defects in dielectric layers other than oxide. Furthermore, growth of a discontinuous layer may be achieved with a material other than a nitride using CVD techniques.

7. 发明授权

US4927780A Encapsulation method for localized oxidation of silicon 失效
标题翻译：硅局部氧化的封装方法
公开(公告)号：US4927780A
公开(公告)日：1990-05-22
申请号：US415685
申请日：1989-10-02
申请人： Scott S. Roth , Bich-Yen Nguyen , Philip J. Tobin , Wayne Ray , E. Petyr Wachholz , Glenn Wissen
发明人： Scott S. Roth , Bich-Yen Nguyen , Philip J. Tobin , Wayne Ray , E. Petyr Wachholz , Glenn Wissen
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/32 , H01L21/7621
摘要： An improved LOCOS isolation process is disclosed wherein an oxidizable layer is conformably dieposited to overlie a silicon nitride oxidation mask. In accordance with one embodiment of the invention, a composite layer comprising a buffer layer and an oxidation resistant material is patterned to form an oxidation mask on a silicon substrate. A layer of an oxidizable material is conformably deposited to overlie the oxidation mask. During the oxidation process used to form electrical isolation structures in the substrate, a substantial reduction in lateral oxidation encroachment is realized.

8. 发明授权

US4740483A Selective LPCVD tungsten deposition by nitridation of a dielectric 失效
标题翻译：通过电介质的氮化选择性LPCVD钨沉积
公开(公告)号：US4740483A
公开(公告)日：1988-04-26
申请号：US20847
申请日：1987-03-02
申请人： Philip J. Tobin
发明人： Philip J. Tobin
IPC分类号： H01L21/314 , H01L21/768 , H01L21/443
CPC分类号： H01L21/76879 , H01L21/3144 , Y10S148/112 , Y10S148/133
摘要： A process for selective deposition of a refractory metal such as tungsten at high temperatures and low pressure via chemical vapor deposition during semiconductor device manufacturing is provided. A dielectric layer is nitrided by chemical deposition of a nitrogen bearing gas prior to LPCVD deposition of tungsten for purposes such as contact metallization of current conducting electrodes and current controlling electrodes of transistors. Since nitridation of the dielectric is a surface chemical reaction and not an addition of material to the dielectric, no additional complexity is introduced into the LPCVD process. The refractory metal does not substantially deposit on the nitrided dielectric thereby providing selective metal deposition.
摘要翻译：提供了一种在半导体器件制造期间通过化学气相沉积在高温和低压下选择性沉积诸如钨的难熔金属的方法。在LPCVD沉积钨之前，通过氮气承载气体的化学沉积来对电介质层进行氮化，用于例如电流传导电极的接触金属化和晶体管的电流控制电极。由于电介质的氮化是表面化学反应而不是向电介质添加材料，所以在LPCVD工艺中不会引入额外的复杂性。难熔金属基本上不沉积在氮化电介质上，从而提供选择性金属沉积。

9. 发明授权

US06423632B1 Semiconductor device and a process for forming the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06423632B1
公开(公告)日：2002-07-23
申请号：US09621804
申请日：2000-07-21
申请人： Srikanth B. Samavedam , Philip J. Tobin , William J. Taylor, Jr.
发明人： Srikanth B. Samavedam , Philip J. Tobin , William J. Taylor, Jr.
IPC分类号： H01L2144
CPC分类号： H01L29/49 , H01L21/2807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a process for forming the device includes a conductor that overlies an insulating layer. In one embodiment, the conductor includes a first conductive portion, a second conductive portion, and a third conductive portion. The second conductive portion lies between the first and third conductive portions. The first conductive portion includes a first element, and the third conductive portion includes a metal and silicon without a significant amount of the first element. In another embodiment, the conductor is a gate electrode or a capacitor electrode. The conductor includes a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion. The second conductive portion lies between the first and third conductive portions and has a different composition compared to the first, third, and fourth conductive portion. The third conductive portion lies between the second and fourth conductive portions and has a different composition compared to the first and fourth conductive portions.
摘要翻译：半导体器件和用于形成器件的工艺包括覆盖在绝缘层上的导体。在一个实施例中，导体包括第一导电部分，第二导电部分和第三导电部分。第二导电部分位于第一和第三导电部分之间。第一导电部分包括第一元件，并且第三导电部分包括没有大量第一元件的金属和硅。在另一个实施例中，导体是栅电极或电容器电极。导体包括第一导电部分，第二导电部分，第三导电部分和第四导电部分。第二导电部分位于第一和第三导电部分之间，并且与第一，第三和第四导电部分相比具有不同的组成。第三导电部分位于第二和第四导电部分之间，并且与第一和第四导电部分相比具有不同的组成。

10. 发明授权

US6084279A Semiconductor device having a metal containing layer overlying a gate dielectric 失效
标题翻译：具有覆盖在栅极电介质上的含金属层的半导体器件
公开(公告)号：US6084279A
公开(公告)日：2000-07-04
申请号：US831287
申请日：1997-03-31
申请人： Bich-Yen Nguyen , J. Olufemi Olowolafe , Bikas Maiti , Olubunmi Adetutu , Philip J. Tobin
发明人： Bich-Yen Nguyen , J. Olufemi Olowolafe , Bikas Maiti , Olubunmi Adetutu , Philip J. Tobin
IPC分类号： H01L29/78 , H01L21/28 , H01L21/285 , H01L21/768 , H01L21/8234 , H01L21/8244 , H01L23/31 , H01L29/49 , H01L21/338
CPC分类号： H01L27/11 , H01L21/28044 , H01L21/28088 , H01L21/28568 , H01L21/76895 , H01L21/82345 , H01L23/3171 , H01L29/4925 , H01L29/4966 , H01L2924/0002
摘要： Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).
摘要翻译：金属半导体氮化物栅电极（40,70）形成用于半导体器件（60）。栅电极（40,70）可以通过溅射沉积，低压化学气相沉积（LPCVD）或等离子体增强化学气相沉积（PECVD）来形成。预期这些材料将类似于含硅化合物蚀刻，并且可以在传统的基于卤化物的蚀刻化学中进行蚀刻。金属半导体氮化物栅电极（40,70）相对稳定，可以形成为比传统栅极电极（40,70）更靠近工作功能，并且靠近用于衬底（12）的材料的带隙中间的功函数。

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