专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070217276A1 FUSE LATCH CIRCUIT, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY SYSTEM 审中-公开
标题翻译：保险丝锁存电路，半导体器件和半导体存储器系统
公开(公告)号：US20070217276A1
公开(公告)日：2007-09-20
申请号：US11687084
申请日：2007-03-16
申请人： Yoshinori Sugisawa
发明人： Yoshinori Sugisawa
IPC分类号： G11C17/18 , G11C29/00 , G11C17/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C29/812 , G11C2207/107
摘要： A data storing fuse element unit includes a plurality of fuse elements, stores data in the respective fuse elements in a bit unit in accordance with presence and absence of cutting of fuse elements, and a latch circuit unit latches the stored data by the bit unit. A logic information storing fuse element unit stores logic information of whether output logic of the data stored in the fuse elements is to be inverted or not. A data selecting unit selects any one of data latched in the latch circuit unit and data with the output logic of the data latched in the latch circuit unit inverted in a logic inverting unit, in accordance with logic information of the logic information storing fuse element unit and outputs the data.
摘要翻译：数据存储熔丝元件单元包括多个熔丝元件，根据存在和不存在熔丝元件的切割，以位单元存储各个熔丝元件中的数据，并且锁存电路单元通过位单元锁存存储的数据。逻辑信息存储熔丝元件单元存储存储在熔丝元件中的数据的输出逻辑是否被反转的逻辑信息。数据选择单元根据逻辑信息存储熔丝元件单元的逻辑信息，选择在锁存电路单元中锁存的数据中的任何一个以及锁存在逻辑反相单元中的锁存电路单元中锁存的数据的输出逻辑的数据并输出数据。

2. 发明授权

US06928594B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06928594B2
公开(公告)日：2005-08-09
申请号：US09821163
申请日：2001-03-28
申请人： Toshiyuki Kouchi , Yoshinori Sugisawa , Takehiko Hojo
发明人： Toshiyuki Kouchi , Yoshinori Sugisawa , Takehiko Hojo
IPC分类号： G11C11/401 , G11C7/10 , G11C29/00 , G11C29/02 , G11C29/10 , G11C29/14 , G11C29/26 , G11C29/46 , H01L21/822 , H01L27/04 , G06F12/00 , G06F13/00
CPC分类号： G11C7/1057 , G11C7/1012 , G11C7/1051 , G11C29/10 , G11C29/14 , G11C29/26 , G11C29/46 , G11C2207/104
摘要： A logic in DRAM LSI is disclosed, which comprises a plurality of DRAM circuits, a control circuit that receives a test control signal to perform a test control in which the plurality of RAM circuits are tested while the access to the plurality of DRAM circuits is subsequently changed for each row, an input selector that is controlled by the control circuit and inputs a DRAM macro signal to the plurality of DRAM circuits at the time of a test, and an output selector that is controlled by the control circuit, and outputs output signals of the plurality of DRAM circuits sequentially to a macro output terminal at the time of the test. According to the DRAM integrated LSI, a test time required to test the plurality of DRAM circuits integrated in the LSI is shortened. Moreover, data that is read from the plurality of DRAM circuits is transferred in a high speed.
摘要翻译：公开了DRAM LSI中的逻辑，其包括多个DRAM电路，控制电路，其接收测试控制信号以执行其中多个RAM电路被测试的测试控制，同时对多个DRAM电路的访问随后对于每行而言，由控制电路控制的输入选择器，并且在测试时将DRAM宏信号输入到多个DRAM电路，以及由控制电路控制的输出选择器，并输出输出信号的多个DRAM电路在测试时顺序地送到宏输出端。根据DRAM集成LSI，集成在LSI中的多个DRAM电路的测试所需的测试时间缩短。此外，从多个DRAM电路读取的数据被高速传送。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式