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1. 发明申请

US20060077732A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20060077732A1
公开(公告)日：2006-04-13
申请号：US11076633
申请日：2005-03-09
申请人： Takehiko Hojo
发明人： Takehiko Hojo
IPC分类号： G11C7/00
CPC分类号： G06F11/1008 , G11C7/1006 , G11C2207/104
摘要： A semiconductor integrated circuit device includes a first memory circuit which stores normal data, a second memory circuit which stores determination information used to determine whether a value of the normal data is changed or not, and a determination circuit which determines whether a value of the normal data is changed or not based on the determination information. The capacitance of a data storage node of the second memory circuit is larger than that of a data storage node of the first memory circuit.
摘要翻译：一种半导体集成电路器件，包括存储正常数据的第一存储器电路，存储用于确定正常数据的值是否改变的确定信息的第二存储器电路，以及确定正常值的值的确定电路基于确定信息改变或不改变数据。第二存储器电路的数据存储节点的电容大于第一存储器电路的数据存储节点的电容。

2. 发明授权

US06985395B2 Semiconductor memory device and method of testing the device 失效
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US06985395B2
公开(公告)日：2006-01-10
申请号：US10884105
申请日：2004-07-01
申请人： Takanori Yoshimatsu , Takehiko Hojo , Kaoru Tokushige
发明人： Takanori Yoshimatsu , Takehiko Hojo , Kaoru Tokushige
IPC分类号： G11C7/00
CPC分类号： G11C29/44
摘要： A semiconductor memory device is disclosed, which includes a memory cell array including memory cells arranged in rows and columns, a word line, a bit line, a row decoder and a column decoder, a sense amplifier provided for each of the columns of the memory cell array, a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode, a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode, a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit, and a first comparison result register configured to store a comparison result of the first comparison circuit.
摘要翻译：公开了一种半导体存储器件，其包括存储单元阵列，该存储单元阵列包括以行和列排列的存储单元，字线，位线，行解码器和列解码器，为存储器的每列提供的读出放大器单元阵列，写锁存电路，被配置为存储外部输入数据，并以测试模式设置读出放大器中的一行存储单元阵列的数据;读锁存器电路，被配置为存储从存储器读取的一行数据单元阵列，并且在测试模式下设置在读出放大器中，第一比较电路，被配置为将存储在写入锁存电路中的数据与存储在读取锁存电路中的数据进行比较;第一比较结果寄存器，被配置为存储比较结果第一个比较电路。

3. 发明授权

US06949969B2 Semiconductor device having relief circuit for relieving defective portion 失效
标题翻译：具有用于消除缺陷部分的释放电路的半导体装置
公开(公告)号：US06949969B2
公开(公告)日：2005-09-27
申请号：US10414226
申请日：2003-04-16
申请人： Kenichiro Mimoto , Takehiko Hojo
发明人： Kenichiro Mimoto , Takehiko Hojo
IPC分类号： G01R31/28 , G11C29/00 , G11C29/04 , H01H85/00 , H01L21/00 , H01L21/82 , H01L21/822 , H01L23/525 , H01L27/00 , H01L27/04 , H02B1/26
CPC分类号： G11C29/787 , G11C29/72 , G11C29/808 , G11C29/838
摘要： A semiconductor device includes a relief-subject circuit, a relief circuit, and a plurality of fuse elements. The relief-subject circuit implements a predetermined function. The relief circuit is provided to relieve the relief-subject circuit in order to implement the predetermined function. The plurality of fuse elements are provided corresponding to the relief circuit in order to replace the relief-subject circuit with the relief circuit, thus storing information to specify the relief-subject circuit when this relief-subject circuit is replaced by the relief circuit.
摘要翻译：半导体器件包括解除对象电路，浮雕电路和多个熔丝元件。救济对象电路实现预定的功能。提供释放电路以便释放救济对象电路以实现预定功能。多个保险丝元件相应于释放电路设置，以便用释放电路代替救济对象电路，从而存储当释放电路被释放电路代替时指定救济对象电路的信息。

4. 发明申请

US20050068816A1 Semiconductor memory device and method of testing the device 失效
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US20050068816A1
公开(公告)日：2005-03-31
申请号：US10884105
申请日：2004-07-01
申请人： Takanori Yoshimatsu , Takehiko Hojo , Kaoru Tokushige
发明人： Takanori Yoshimatsu , Takehiko Hojo , Kaoru Tokushige
IPC分类号： G11C29/12 , G11C11/401 , G11C29/04 , G11C29/44 , G11C7/00
CPC分类号： G11C29/44
摘要： A semiconductor memory device is disclosed, which comprises a memory cell array including memory cells arranged in rows and columns, a word line, a bit line, a row decoder and a column decoder, a sense amplifier provided for each of the columns of the memory cell array, a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode, a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode, a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit, and a first comparison result register configured to store a comparison result of the first comparison circuit.
摘要翻译：公开了一种半导体存储器件，其包括存储单元阵列，该存储单元阵列包括以行和列排列的存储单元，字线，位线，行解码器和列解码器，为存储器的每列提供的读出放大器单元阵列，写锁存电路，被配置为存储外部输入数据，并以测试模式设置读出放大器中的一行存储单元阵列的数据;读锁存器电路，被配置为存储从存储器读取的一行数据单元阵列，并且在测试模式下设置在读出放大器中，第一比较电路，被配置为将存储在写入锁存电路中的数据与存储在读取锁存电路中的数据进行比较;第一比较结果寄存器，被配置为存储比较结果第一个比较电路。

5. 发明授权

US08339830B2 Nonvolatile semiconductor storage 有权
标题翻译：非易失性半导体存储
公开(公告)号：US08339830B2
公开(公告)日：2012-12-25
申请号：US13233320
申请日：2011-09-15
申请人： Hideaki Yamauchi , Daichi Kaku , Takehiko Hojo
发明人： Hideaki Yamauchi , Daichi Kaku , Takehiko Hojo
IPC分类号： G11C17/00
CPC分类号： G11C11/5692 , G11C17/16 , G11C17/18
摘要： According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A sense amplifier is provided for the each memory cell and determines, based on data stored in the n anti-fuse elements, three or more values of readout levels.
摘要翻译：根据一个实施例，使用场效应晶体管配置存储单元，并且包括n个反熔丝元件，其一端共同连接。编程电压选择电路在n个反熔丝元件中选择施加了编程电压的反熔丝元件。为每个存储器单元提供读出放大器，并且基于存储在n个反熔丝元件中的数据确定三个或更多个读出电平值。

6. 发明申请

US20120243357A1 NONVOLATILE SEMICONDUCTOR STORAGE 有权
标题翻译：非挥发性半导体存储
公开(公告)号：US20120243357A1
公开(公告)日：2012-09-27
申请号：US13233320
申请日：2011-09-15
申请人： Hideaki Yamauchi , Daichi Kaku , Takehiko Hojo
发明人： Hideaki Yamauchi , Daichi Kaku , Takehiko Hojo
IPC分类号： G11C7/06
CPC分类号： G11C11/5692 , G11C17/16 , G11C17/18
摘要： According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A sense amplifier is provided for the each memory cell and determines, based on data stored in the n anti-fuse elements, three or more values of readout levels.
摘要翻译：根据一个实施例，使用场效应晶体管配置存储单元，并且包括n个反熔丝元件，其一端共同连接。编程电压选择电路在n个反熔丝元件中选择施加了编程电压的反熔丝元件。为每个存储器单元提供读出放大器，并且基于存储在n个反熔丝元件中的数据确定三个或更多个读出电平值。

7. 发明授权

US07908527B2 Semiconductor integrated circuit and redundancy method thereof 有权
标题翻译：半导体集成电路及其冗余方法
公开(公告)号：US07908527B2
公开(公告)日：2011-03-15
申请号：US12186899
申请日：2008-08-06
申请人： Koji Kohara , Takehiko Hojo
发明人： Koji Kohara , Takehiko Hojo
IPC分类号： G11C29/00
CPC分类号： G11C29/848 , G11C29/802
摘要： A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.
摘要翻译：半导体集成电路包括主存储单元阵列，冗余存储单元阵列，存储器宏和修复信息传送电路。维修信息分析电路取出传送的单元修复信息的修复信息，将修复信息输出到具有冗余修复机构的存储器宏，并通过存储器宏的冗余修复机制将存储器宏进行冗余修复处理所传送的单元修复信息的存储器识别信息与存储在非易失性存储元件中的存储器识别信息一致。

8. 发明申请

US20090044045A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND REDUNDANCY METHOD THEREOF 有权
标题翻译：半导体集成电路及其冗余方法
公开(公告)号：US20090044045A1
公开(公告)日：2009-02-12
申请号：US12186899
申请日：2008-08-06
申请人： Koji Kohara , Takehiko Hojo
发明人： Koji Kohara , Takehiko Hojo
IPC分类号： G06F11/20
CPC分类号： G11C29/848 , G11C29/802
摘要： A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.
摘要翻译：半导体集成电路包括主存储单元阵列，冗余存储单元阵列，存储器宏和修复信息传送电路。维修信息分析电路取出传送的单元修复信息的修复信息，将修复信息输出到具有冗余修复机构的存储器宏，并通过存储器宏的冗余修复机制将存储器宏进行冗余修复处理所传送的单元修复信息的存储器识别信息与存储在非易失性存储元件中的存储器识别信息一致。

9. 发明申请

US20080284494A1 FUSE DEVICE, METHOD FOR WRITING DATA, METHOD FOR READING DATA, AND METHOD FOR WRITING AND READING DATA 审中-公开
标题翻译：保险丝装置，用于写入数据的方法，读取数据的方法以及用于写入和读取数据的方法
公开(公告)号：US20080284494A1
公开(公告)日：2008-11-20
申请号：US12118033
申请日：2008-05-09
申请人： Hideaki Yamauchi , Akikuni Sato , Takehiko Hojo
发明人： Hideaki Yamauchi , Akikuni Sato , Takehiko Hojo
IPC分类号： H01H37/76
CPC分类号： H01L27/101 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse device includes a plurality of serially connected fuse elements whose number is n (n is an integer of two or more), a power source connected to one end of a first fuse element that is a top of the n serially connected fuse elements, and a plurality of program control transistors. Each of the program control transistors is connected to each of nodes between the fuse elements, and to an end of the n-th fuse element, respectively.
摘要翻译：保险丝装置包括多个串联连接的熔丝元件，其数量为n（n为2以上的整数），连接到作为n个串联连接的熔丝元件的顶部的第一熔丝元件的一端的电源，和多个程序控制晶体管。每个编程控制晶体管分别连接到熔丝元件之间的每个节点，并分别连接到第n个熔丝元件的端部。

10. 发明申请

US20060002205A1 Semiconductor device having relief circuit for relieving defective portion 审中-公开
标题翻译：具有用于消除缺陷部分的释放电路的半导体装置
公开(公告)号：US20060002205A1
公开(公告)日：2006-01-05
申请号：US11178469
申请日：2005-07-12
申请人： Kenichiro Mimoto , Takehiko Hojo
发明人： Kenichiro Mimoto , Takehiko Hojo
IPC分类号： G11C29/00
CPC分类号： G11C29/787 , G11C29/72 , G11C29/808 , G11C29/838
摘要： A semiconductor device includes a relief-subject circuit, a relief circuit, and a plurality of fuse elements. The relief-subject circuit implements a predetermined function. The relief circuit is provided to relieve the relief-subject circuit in order to implement the predetermined function. The plurality of fuse elements are provided corresponding to the relief circuit in order to replace the relief-subject circuit with the relief circuit, thus storing information to specify the relief-subject circuit when this relief-subject circuit is replaced by the relief circuit.
摘要翻译：半导体器件包括解除对象电路，浮雕电路和多个熔丝元件。救济对象电路实现预定的功能。提供释放电路以便释放救济对象电路以实现预定功能。多个保险丝元件相应于释放电路设置，以便用释放电路代替救济对象电路，从而存储当释放电路被释放电路代替时指定救济对象电路的信息。

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