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1. 发明授权

US5208487A RS flip-flop 失效
标题翻译： RS触发器
公开(公告)号：US5208487A
公开(公告)日：1993-05-04
申请号：US862661
申请日：1992-04-01
申请人： Yoshinori Matsuura , Shinichi Nakagawa , Tetsuya Matsumura
发明人： Yoshinori Matsuura , Shinichi Nakagawa , Tetsuya Matsumura
IPC分类号： H03K3/037 , H03K3/356
CPC分类号： H03K3/037 , H03K3/356017 , H03K3/356069
摘要： A logic circuit outputs a logic signal in response to set inputs and a reset input. This logic signal is applied to output terminals through a latch circuit. When outputs Q and Q of the RS flip-flop maintain a previous state, the latch circuit is activated by a control signal applied from an OR gate to hold a previous logic signal received from the logic circuit. Thus, the logic circuit and latch circuit are arranged on a signal path from input terminals to output terminals. These logic circuit and latch circuit do not include a series connection of transistors and, therefore, is operable at high speed in response to the inputs. Consequently, the outputs Q and Q have excellent response characteristics relative to the set and reset inputs, to enable a high-speed operation.
摘要翻译：逻辑电路根据设定输入和复位输入输出逻辑信号。该逻辑信号通过锁存电路施加到输出端子。当RS触发器的输出Q和＆amp; upbar＆Q保持先前状态时，锁存电路由从或门施加的控制信号激活，以保持从逻辑电路接收到的先前的逻辑信号。因此，逻辑电路和锁存电路被布置在从输入端子到输出端子的信号路径上。这些逻辑电路和锁存电路不包括晶体管的串联连接，因此可以响应于输入以高速操作。因此，输出Q和＆amp; upbar＆Q相对于设定和复位输入具有优异的响应特性，以实现高速运行。

2. 发明授权

US06687299B2 Motion estimation method and apparatus for interrupting computation which is determined not to provide solution 有权
标题翻译：用于中断计算的运动估计方法和装置，其被确定为不提供解决方案
公开(公告)号：US06687299B2
公开(公告)日：2004-02-03
申请号：US09261171
申请日：1999-03-03
申请人： Toyohiko Yoshida , Kazuya Ishihara , Yoshinori Matsuura , Tetsuya Matsumura , Vasily Moshnyaga
发明人： Toyohiko Yoshida , Kazuya Ishihara , Yoshinori Matsuura , Tetsuya Matsumura , Vasily Moshnyaga
IPC分类号： H04B166
CPC分类号： H04N5/145 , G06T7/238 , G06T2207/10016 , H04N19/51 , H04N19/557
摘要： A motion estimation method capable of setting an optimum threshold value and allowing high speed processing includes the steps of: sequentially selecting one of blocks to be searched from a search range; sequentially calculating a difference between corresponding sample values of a reference block and one of blocks to be searched and accumulating an absolute value of difference; comparing an intermediate result of an accumulation value and a prescribed threshold value for a prescribed number of samples and interrupting the step of accumulating the absolute value of difference when the intermediate result exceeds the prescribed threshold value; and making one of blocks to be searched having a minimum final result of the accumulation value correspond to the reference block. The prescribed threshold value is dependent on the reference block. It is noted that the motion estimation apparatus is also disclosed.
摘要翻译：能够设定最佳阈值并允许高速处理的运动估计方法包括以下步骤：从搜索范围顺序选择要搜索的块之一; 顺序地计算参考块的对应样本值与要搜索的块中的一个的差值，并累加差值的绝对值; 比较规定数量样本的累积值和规定阈值的中间结果，并且当中间结果超过规定阈值时中断累积差分绝对值的步骤; 并且使具有累积值的最小最终结果的要搜索的块之一对应于参考块。规定的阈值取决于参考块。注意，还公开了运动估计装置。

3. 发明授权

US06968011B2 Motion vector detecting device improved in detection speed of motion vectors and system employing the same devices 失效
标题翻译：运动矢量检测装置提高运动矢量的检测速度和采用相同装置的系统
公开(公告)号：US06968011B2
公开(公告)日：2005-11-22
申请号：US10155993
申请日：2002-05-29
申请人： Satoshi Kumaki , Tetsuya Matsumura , Atsuo Hanami , Yoshinori Matsuura
发明人： Satoshi Kumaki , Tetsuya Matsumura , Atsuo Hanami , Yoshinori Matsuura
IPC分类号： H04N19/50 , H04N5/14 , H04N19/503 , H04N19/543 , H04N19/57 , H04N7/12
CPC分类号： H04N5/145 , H04N19/436 , H04N19/51
摘要： The control circuit controls output of template block data held in the input section such that a plurality of operation units within the operation section are provided with data of unadjacent template blocks that are different from each other. The operation units within the operation section detect motion vectors according to the template block data provided thereto. Thus, motion vector detection in the template blocks except for those in a region on a display screen requiring no motion vector detection is distributed in the plurality of operation units. Accordingly, the motion vector search can be performed in a wider range in a vertical or horizontal direction than in the conventional case within the same operation time.
摘要翻译：控制电路控制保持在输入部分中的模板块数据的输出，使得操作部分内的多个操作单元被提供有彼此不同的不相邻模板块的数据。操作部分内的操作单元根据提供给它的模板块数据来检测运动矢量。因此，除了不需要运动矢量检测的显示画面上的区域中的模板块中的运动矢量检测分布在多个运算单元中。因此，在相同的动作时间内，与现有的情况相比，可以在比垂直方向或水平方向更宽的范围内进行运动矢量搜索。

4. 发明授权

US6141451A Image coding method and apparatus 失效
标题翻译：图像编码方法及装置
公开(公告)号：US6141451A
公开(公告)日：2000-10-31
申请号：US982427
申请日：1997-12-02
申请人： Satoshi Kumaki , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Yoshinori Matsuura , Atsuo Hanami
发明人： Satoshi Kumaki , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Yoshinori Matsuura , Atsuo Hanami
IPC分类号： H04N19/50 , G06T9/00 , H03M7/36 , H04N19/42 , H04N19/423 , H04N19/46 , H04N19/503 , H04N19/51 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/80 , H04N19/87 , H04N19/91 , G06K9/36
CPC分类号： G06T9/004
摘要： Disclosed is an image coding method and apparatus for preventing a coding quantity of coding data from being increased when a redundancy between image planes is low. A selector outputs either an optimum motion vector output from a motion vector detecting device or a motion vector output from a motion vector storing section to a real time image coding device for performing coding on the basis of an evaluation value output from the motion vector detecting device. If it is decided, according to the evaluation value, that a redundancy between a reference image plane and a coding object image plane is low, the motion vector is selected so that the coding quantity of the coding data can be prevented from being increased.
摘要翻译：公开了一种图像编码方法和装置，用于在图像平面之间的冗余度低时防止编码数据的编码量增加。选择器输出从运动矢量检测装置输出的最佳运动矢量或从运动矢量存储部分输出的运动矢量到实时图像编码装置，用于根据从运动矢量检测装置输出的评估值进行编码。如果根据评估值确定参考图像平面和编码对象图像平面之间的冗余度低，则选择运动矢量，使得可以防止编码数据的编码量增加。

5. 发明授权

US6122317A Motion vector detector 失效
标题翻译：运动矢量检测器
公开(公告)号：US6122317A
公开(公告)日：2000-09-19
申请号：US975207
申请日：1997-11-20
申请人： Atsuo Hanami , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Satoshi Kumaki , Yoshinori Matsuura
发明人： Atsuo Hanami , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Satoshi Kumaki , Yoshinori Matsuura
IPC分类号： H04N19/50 , H03M7/30 , H04N19/436 , H04N19/46 , H04N19/463 , H04N19/503 , H04N19/51 , H04N19/517 , H04N19/57 , H04N19/70 , H04N7/12 , H04B1/66
CPC分类号： H04N19/105 , H04N19/112 , H04N19/137 , H04N19/51 , H04N19/517 , H04N19/56
摘要： An evaluation value operation part computes evaluation values of a template block and a search window block in accordance with respective ones of a plurality of predictive modes in parallel with each other, and a candidate vector determination part decides candidate vectors indicating optimum vectors in accordance with the computed evaluation values and on the basis of priority levels from a priority generation part. In accordance with these candidate vectors, an optimum vector decision part decides the optimum vectors for the respective predictive modes. Thus provided is an image coding system which can reduce the amount of codes of motion vectors with excellent picture quality.
摘要翻译：评估值操作部分根据多个预测模式中的各自相互并行地计算模板块和搜索窗口块的评估值，并且候选向量确定部分根据所述候选向量确定部分来确定表示最佳向量的候选向量计算的评估值，并根据优先级生成部分的优先级。根据这些候选向量，最佳矢量判定部分决定各个预测模式的最佳向量。这样提供了一种图像编码系统，其可以减少具有优良图像质量的运动矢量的编码量。

6. 发明授权

US5303353A Data transfer system 失效
标题翻译：数据传输系统
公开(公告)号：US5303353A
公开(公告)日：1994-04-12
申请号：US862660
申请日：1992-04-01
申请人： Yoshinori Matsuura , Shinichi Uramoto , Tetsuya Matsumura
发明人： Yoshinori Matsuura , Shinichi Uramoto , Tetsuya Matsumura
IPC分类号： G06F13/28 , G06F13/38 , G06F13/40
CPC分类号： G06F13/4018
摘要： A data bus has a bit length of 2 words, and is divided into two bit groups, each of which corresponds to one word. Therefore, the data bus can simultaneously transfer data of two words. A register, a data operation part of a CPU, a RAM and a ROM is connected to the data bus. Even if there is generated data of two words to be transferred in these registers, the data operation part, the RAM and the ROM, the data bus can simultaneously transfer the data. In order to prevent conflict of data on the data bus, there are provided a bus driver, a multiplexer and a bus selector.
摘要翻译：数据总线具有2个字的位长度，并被分成两个位组，每个位对应一个字。因此，数据总线可以同时传输两个字的数据。寄存器，CPU的数据操作部分，RAM和ROM连接到数据总线。即使存在要在这些寄存器中传送的两个字的数据，数据操作部分，RAM和ROM，数据总线也可以同时传送数据。为了防止数据总线上的数据冲突，提供了总线驱动器，多路复用器和总线选择器。

7. 发明授权

US06516031B1 Motion vector detecting device 失效
标题翻译：运动矢量检测装置
公开(公告)号：US06516031B1
公开(公告)日：2003-02-04
申请号：US09084504
申请日：1998-05-27
申请人： Kazuya Ishihara , Atsuo Hanami , Tetsuya Matsumura , Satoshi Kumaki , Hiroshi Segawa , Yoshinori Matsuura , Stefan Scotzniovsky
发明人： Kazuya Ishihara , Atsuo Hanami , Tetsuya Matsumura , Satoshi Kumaki , Hiroshi Segawa , Yoshinori Matsuura , Stefan Scotzniovsky
IPC分类号： H04N732
CPC分类号： H04N5/145 , G06T7/231 , G06T2200/28 , G06T2207/10016
摘要： Element processors (PE00 to PE33) included in a processor array (7) store pixel values of a search window, shifting them forward. Further, only hatched element processors (PE00, PE02, PE11, PE13, PE20, PE22, PE31, PE33) store pixel values of a template block, and compare them with the pixel values in the search to evaluate a similarity of pixel values. In other words, the pixel values of the template block are skipped and the pixel values which are left after skipping are compared. Therefore, it is possible to cut a hardware volume.
摘要翻译：包含在处理器阵列（7）中的元件处理器（PE00至PE33）存储搜索窗口的像素值，将它们向前移位。此外，只有阴影元素处理器（PE00，PE02，PE11，PE13，PE20，PE22，PE31，PE33）存储模板块的像素值，并将其与搜索中的像素值进行比较，以评估像素值的相似度。换句话说，跳过模板块的像素值，并比较跳过之后留下的像素值。因此，可以削减硬件容量。

8. 发明授权

US06674798B2 Motion vector detecting device capable of accommodating a plurality of predictive modes 失效
标题翻译：能够适应多种预测模式的运动矢量检测装置
公开(公告)号：US06674798B2
公开(公告)日：2004-01-06
申请号：US09961139
申请日：2001-09-24
申请人： Kazuya Ishihara , Shinichi Uramoto , Shinichi Nakagawa , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami
发明人： Kazuya Ishihara , Shinichi Uramoto , Shinichi Nakagawa , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami
IPC分类号： H04N736
CPC分类号： H04N5/145 , G06T7/223 , G06T7/231 , G06T2207/10016 , H04N19/433 , H04N19/51
摘要： A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode. It is possible to simultaneously detect motion vectors according to a plurality of predictive modes. It is possible to detect motion vectors employed for moving image predictive compensation in accordance with a plurality of predictive modes at a high speed with a small hardware volume.
摘要翻译：处理器阵列包括对应于作为当前图像像素块的模板块的各个像素的矩阵排列的元件处理器。每个元素处理器存储作为对应的参考图像像素块的搜索窗口块的像素数据，并获得关于模板块像素数据的评估函数值分量。求和部分根据多种预测模式对从处理器阵列的相应元件处理器接收的评估函数分量进行排序，并对各种类型的组件求和，以形成各个预测模式的评估函数值。比较部分比较从每个预测模式的求和部分接收的评估函数值，以确定提供最佳相似度的位移矢量作为每个预测模式的运动矢量。可以根据多种预测模式同时检测运动矢量。根据具有小硬件体积的高速的多种预测模式，可以检测用于运动图像预测补偿的运动矢量。

9. 发明授权

US5400295A Semiconductor integrated circuit device and semiconductor memory device 失效
公开(公告)号：US5400295A
公开(公告)日：1995-03-21
申请号：US976055
申请日：1992-11-13
申请人： Tetsuya Matsumura , Satoshi Kumaki , Shinichi Nakagawa
发明人： Tetsuya Matsumura , Satoshi Kumaki , Shinichi Nakagawa
IPC分类号： G11C11/417 , G11C7/10 , H01L27/10 , H03K3/356 , G11C11/34
CPC分类号： H03K3/356173 , G11C7/1051 , H03K3/356121
摘要： In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

10. 发明授权

US6125432A Image process apparatus having a storage device with a plurality of banks storing pixel data, and capable of precharging one bank while writing to another bank 失效
标题翻译：具有存储装置的图像处理装置具有存储像素数据的多个存储体，并且能够在写入另一个存储体时对一个存储体进行预充电
公开(公告)号：US6125432A
公开(公告)日：2000-09-26
申请号：US903348
申请日：1997-07-30
申请人： Atsuo Hanami , Shinichi Nakagawa , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Satoshi Kumaki
发明人： Atsuo Hanami , Shinichi Nakagawa , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Satoshi Kumaki
IPC分类号： G06F12/06 , G06F12/00 , G06T1/60 , G09G5/39 , G09G5/399 , G11C11/401 , G11C11/407 , H04N7/50 , G06F12/02
CPC分类号： G09G5/39 , H04N19/423 , H04N19/61 , G09G2340/02 , G09G2360/123 , G09G5/399
摘要： Screen data consists of two sets of field data. Each set of field data is divided into a plurality of data blocks which has four rows of pixel data corresponding to four rows of pixels vertically arranged. Every data block corresponding to one set of field data is stored in the first bank (bank0) of a frame buffer memory while that corresponding to the other set of field data is stored in the second bank (bank1). One row address is assigned to each data block. Bank1 is precharged while bank0 is in a write operation and vice versa in order to carry out the precharging operation and the write operation concurrently, so that the pixel data can be transferred at a high data transfer rate and each of two sets of field data can be transferred independently.
摘要翻译：屏幕数据由两组现场数据组成。每组场数据被分成多个数据块，其具有与垂直排列的四行像素对应的四行像素数据。对应于一组场数据的每个数据块被存储在帧缓冲存储器的第一存储体（存储体0）中，而与另一组场数据相对应的数据块存储在第二存储体（存储体1）中）。一行地址分配给每个数据块。 Bank1被预充电，而bank0处于写操作，反之亦然，以便同时执行预充电操作和写操作，使得可以以高数据传输速率传输像素数据，并且两组现场数据可以独立转让

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