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1. 发明授权

US5380704A Superconducting field effect transistor with increased channel length 失效
标题翻译：超导场效应晶体管具有增加的沟道长度
公开(公告)号：US5380704A
公开(公告)日：1995-01-10
申请号：US113006
申请日：1993-08-30
申请人： Yoshinobu Tarutani , Tokuumi Fukazawa , Uki Kabasawa , Kazumasa Takagi , Akira Tsukamoto , Masahiko Hiratani , Toshikazu Nishino
发明人： Yoshinobu Tarutani , Tokuumi Fukazawa , Uki Kabasawa , Kazumasa Takagi , Akira Tsukamoto , Masahiko Hiratani , Toshikazu Nishino
IPC分类号： H01L29/43 , H01L29/49 , H01L29/786 , H01L39/22 , B05D5/12 , H01B12/00
CPC分类号： H01L29/78696 , H01L29/437 , H01L29/4908 , H01L29/78645 , H01L29/7869 , H01L39/146
摘要： Disclosed herein is a superconducting field effect transistor (FET) which has at least an active region formed from a film of oxide normal conductor, a plurality of electrodes formed from a film of oxide superconductor, and a means to control the current which flows between the electrodes through the active region. Having a much greater electrode distance than the conventional superconducting device, it can be produced easily by lithography without resorting to special techniques.
摘要翻译：本发明公开了一种超导场效应晶体管（FET），其至少具有由氧化物正导体膜形成的有源区，由氧化物超导体的膜形成的多个电极，以及控制在氧化物超导体之间流动的电流的装置电极通过有源区。具有比常规超导装置更大的电极距离，其可以通过光刻而容易地制造，而不需要采用特殊技术。

2. 发明授权

US5250506A Superconductive switching element with semiconductor channel 失效
标题翻译：具有半导体通道的超导开关元件
公开(公告)号：US5250506A
公开(公告)日：1993-10-05
申请号：US647234
申请日：1991-01-29
申请人： Shinichiroh Saitoh , Yoshinobu Tarutani , Tokuumi Fukazawa , Masahiko Hiratani , Toshikazu Nishino , Haruhiro Hasegawa , Ushio Kawabe , Kazumasa Takagi , Mitsuo Suga
发明人： Shinichiroh Saitoh , Yoshinobu Tarutani , Tokuumi Fukazawa , Masahiko Hiratani , Toshikazu Nishino , Haruhiro Hasegawa , Ushio Kawabe , Kazumasa Takagi , Mitsuo Suga
IPC分类号： H01L39/14 , H01L39/22 , B05D5/12 , H01B12/00
CPC分类号： H01L39/225 , H01L39/146
摘要： A superconductive element at least comprising first and second superconductive electrodes composed of an oxide superconductor material and a semiconductor film composed of an oxide semiconductor material put between the first and second superconductive electrodes and disposed in adjacent with the first and the second superconductive electrodes, in which the semiconductor film is formed with an oxide comprising rare earth elements other than Pr, Ba and Cu as the main ingredient element or an oxide comprising predetermined amount of rare earth elements other than Pr, predetermined amount of Pr, Ba and Cu as the main ingredient element. Extremely fine size is no more necessary to enable fabrication with the existent fine fabrication technic.
摘要翻译：一种超导元件，至少包括由氧化物超导体材料构成的第一和第二超导电极以及由位于第一和第二超导电极之间并与第一和第二超导电极相邻设置的氧化物半导体材料构成的半导体膜，其中半导体膜由包含除Pr，Ba和Cu之外的稀土元素作为主要成分的氧化物或包含预定量的Pr以外的稀土元素的氧化物形成，预定量的Pr，Ba和Cu作为主要成分元件。非常精细的尺寸不再需要使用现有的精细制造技术进行制造。

3. 发明授权

US5077266A Method of forming weak-link Josephson junction, and superconducting device employing the junction 失效
标题翻译：形成弱连接JOSEPHSON JUNCTION的方法和使用连接的超级设备
公开(公告)号：US5077266A
公开(公告)日：1991-12-31
申请号：US405737
申请日：1989-09-11
申请人： Kazumasa Takagi , Tokuumi Fukazawa , Yoshimi Kawanami , Yuuichi Madokoro , Katsuki Miyauchi , Toshiyuki Aida , Yukio Honda , Masaaki Futamoto , Masahiko Hiratani
发明人： Kazumasa Takagi , Tokuumi Fukazawa , Yoshimi Kawanami , Yuuichi Madokoro , Katsuki Miyauchi , Toshiyuki Aida , Yukio Honda , Masaaki Futamoto , Masahiko Hiratani
IPC分类号： H01L39/22 , H01L39/24
CPC分类号： H01L39/2496 , Y10S505/701 , Y10S505/702 , Y10S505/729 , Y10T29/41
摘要： A weak-link Josephson junction is of the type employing a thin film of an oxide superconductor, in which a crystal grain boundary produced reflecting an artificial crystal defect is utilized as the weak-link junction. The crystal grain boundary is formed concretely by a method in which atoms of different species are deposited on the predetermined part of the surface of a substrate, the predetermined part of the surface of a substrate is disturbed, or parts of different crystal face orientations are formed at the surface of a substrate, whereupon the superconducting thin film is epitaxially grown on the substrate, or by a method in which the predetermined part of the superconducting thin film, epitaxially grown on a substrate, is diffused with atoms of different species hampering a superconductivity, or the predetermined part of the superconducting thin film is disturbed, whereupon the superconducting thin film is annealed.

4. 发明授权

US5914068A Bi-layer oxide ferroelectrics 失效
标题翻译：双层氧化物铁电体
公开(公告)号：US5914068A
公开(公告)日：1999-06-22
申请号：US765575
申请日：1996-12-30
申请人： Masahiko Hiratani , Keiko Kushida , Kazushige Imagawa , Kazumasa Takagi
发明人： Masahiko Hiratani , Keiko Kushida , Kazushige Imagawa , Kazumasa Takagi
IPC分类号： C04B35/453 , C30B29/22
CPC分类号： C04B35/453
摘要： Novel Bi-layer Perovskite ferroelectrics constituted of BiO intermediate layers (17) and pseudo-Perovskite layers (18) stacked alternately are disclosed. The Bi-layer Perovskite ferroelectrics have such a crystal structure which has a fundamental skeleton composed of each intermediate layer (17) consisting of one BiO plane and each pseudo-Perovskite structure (18) consisting of Pb(Zr, Ti)O.sub.3. Since the intermediate layer (17) is constituted of the BiO layer, the ferroelectrics are more excellent in ferroelectric characteristics and thermodynamic stability than known Perovskite ferroelectrics comprising a Bi.sub.2 O.sub.2 layer.
摘要翻译： PCT No.PCT / JP95 / 01205 Sec。 371日期1996年12月30日第 102（e）日期1996年12月30日PCT归档1995年6月16日PCT公布。出版物WO96 / 00704 日期1996年1月11日公开了由交替堆叠的BiO中间层（17）和伪钙钛矿层（18）构成的新型双层钙钛矿型铁电体。双层钙钛矿铁电体具有这样的晶体结构，其具有由由一个BiO平面构成的每个中间层（17）和由Pb（Zr，Ti）O 3组成的每个假钙钛矿结构（18）组成的基本骨架。由于中间层（17）由BiO层构成，所以铁电体的铁电特性和热力学稳定性优于包括Bi 2 O 2层的已知钙钛矿型铁电体。

5. 发明授权

US06833577B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06833577B2
公开(公告)日：2004-12-21
申请号：US10300763
申请日：2002-11-21
申请人： Yuichi Matsui , Masahiko Hiratani
发明人： Yuichi Matsui , Masahiko Hiratani
IPC分类号： H01L27108
CPC分类号： H01L21/022 , C23C16/18 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02183 , H01L21/02194 , H01L21/02271 , H01L21/02356 , H01L21/31604 , H01L21/31637 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L27/10894 , H01L28/40 , H01L28/56 , H01L28/75 , H01L28/90
摘要： The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.
摘要翻译：本发明涉及半导体电容器存储器件的电容器的结构，特别是五氧化二铌。由于五氧化二铌具有600℃以下的低结晶温度，所以五氧化二铌可以通过热处理抑制底部电极和阻挡金属的氧化。然而，根据低温热处理，从CVD源引入到膜中的碳不易氧化或除去。因此，出现漏电流增加的问题。作为电容器的绝缘膜，使用由五氧化二铌膜和五氧化二钽膜构成的层叠膜或由五氧化二铌膜构成的层叠膜。通过使用五氧化二铌膜，可以使电容器的介电常数高，可以降低结晶温度。通过电介质膜的多级形成，可以降低泄漏电流。

6. 发明授权

US06534375B2 METHOD OF FORMING A CAPACITOR IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING A METAL SILICON NITRIDE LAYER TO PROTECT AN UNDERLYING METAL SILICIDE LAYER FROM OXIDATION DURING SUBSEQUENT PROCESSING STEPS 有权
标题翻译：在半导体集成电路器件中形成电容器的方法使用金属硅化物层在后续处理步骤中从氧化物中保护金属硅酸盐层
公开(公告)号：US06534375B2
公开(公告)日：2003-03-18
申请号：US09923406
申请日：2001-08-08
申请人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
发明人： Shinpei Iijima , Yuzuru Ohji , Masato Kunitomo , Masahiko Hiratani , Yuichi Matsui , Hiroyuki Ohta , Yukihiro Kumagai
IPC分类号： H01L21285
CPC分类号： H01L21/02183 , H01L21/02271 , H01L21/02337 , H01L21/02356 , H01L21/31637 , H01L27/10814 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
摘要翻译：形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

7. 发明授权

US06509246B2 Production of semiconductor integrated circuit 失效
公开(公告)号：US06509246B2
公开(公告)日：2003-01-21
申请号：US09877207
申请日：2001-06-11
申请人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
发明人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

8. 发明授权

US08106441B2 Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same 有权
标题翻译：具有多个DRAM存储单元的半导体器件及其制造方法
公开(公告)号：US08106441B2
公开(公告)日：2012-01-31
申请号：US12861407
申请日：2010-08-23
申请人： Satoru Akiyama , Takao Watanabe , Yuichi Matsui , Masahiko Hiratani
发明人： Satoru Akiyama , Takao Watanabe , Yuichi Matsui , Masahiko Hiratani
IPC分类号： H01L27/06
CPC分类号： H01L27/10852 , H01L23/5223 , H01L27/105 , H01L27/1052 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.
摘要翻译： DRAM的存储单元电容器（C3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同层（M3）的金属布线作为其电极，从而能够减少工艺成本通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。

9. 发明申请

US20100314676A1 SEMICONDUCTOR DEVICE HAVING PLURAL DRAM MEMORY CELLS AND A LOGIC CIRCUIT AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：具有PLOR DRAM存储器单元的半导体器件和逻辑电路及其制造方法
公开(公告)号：US20100314676A1
公开(公告)日：2010-12-16
申请号：US12861407
申请日：2010-08-23
申请人： Satoru Akiyama , Takao Watanabe , Yuichi Matsui , Masahiko Hiratani
发明人： Satoru Akiyama , Takao Watanabe , Yuichi Matsui , Masahiko Hiratani
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L23/5223 , H01L27/105 , H01L27/1052 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.
摘要翻译： DRAM的存储单元电容器（C3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同层（M3）的金属布线作为其电极，从而能够减少工艺成本通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。

10. 发明授权

US07804118B2 Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same 失效
公开(公告)号：US07804118B2
公开(公告)日：2010-09-28
申请号：US12635181
申请日：2009-12-10
申请人： Satoru Akiyama , Takao Watanabe , Yuichi Matsui , Masahiko Hiratani
发明人： Satoru Akiyama , Takao Watanabe , Yuichi Matsui , Masahiko Hiratani
IPC分类号： H01L29/78
CPC分类号： H01L27/10852 , H01L23/5223 , H01L27/105 , H01L27/1052 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

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