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1. 发明申请

US20060154447A1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20060154447A1
公开(公告)日：2006-07-13
申请号：US11330996
申请日：2006-01-13
申请人： Yoshimasa Kushima , Tadashi Yamaguchi
发明人： Yoshimasa Kushima , Tadashi Yamaguchi
IPC分类号： H01L21/78 , H01L21/301
CPC分类号： H01L21/78 , H01L2224/96
摘要： A method for manufacturing a semiconductor device comprises the steps of forming protruded electrodes on a plurality chip areas of a semiconductor wafer having the plurality of chip areas and boundary regions formed among the chip areas, both being provided in a surface of the semiconductor wafer, forming a surface-side protective member so as to cover the surface of the semiconductor wafer and the protruded electrodes, removing the semiconductor wafer corresponding to the boundary regions and forming trenches which expose the surface-side protective member, forming a back-side protective member with which the trenches are filled and which covers the back of the semiconductor wafer, and dividing the semiconductor wafer in the boundary regions with widths thinner than those of the trenches in such a manner that the surface-side protective member and the back-side protective member charged into the trenches are left in cut sections.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在具有形成在芯片区域之间的多个芯片区域和边界区域的半导体晶片的多个芯片区域上形成突起电极，两者设置在半导体晶片的表面中，形成表面侧保护构件，以覆盖半导体晶片和突出电极的表面，去除对应于边界区域的半导体晶片，并形成暴露表面侧保护构件的沟槽，形成背面保护构件，形成背面保护构件沟槽被填充并且覆盖半导体晶片的背面，并且以这样的方式将半导体晶片划分在具有比沟槽更薄的边界区域的边界区域中，使得表面侧保护构件和背面保护构件装入沟槽的部分留在切割部分。

2. 发明授权

US07763528B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07763528B2
公开(公告)日：2010-07-27
申请号：US11330996
申请日：2006-01-13
申请人： Yoshimasa Kushima , Tadashi Yamaguchi
发明人： Yoshimasa Kushima , Tadashi Yamaguchi
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L2224/96
摘要： A method for manufacturing a semiconductor device includes forming protruded electrodes on a plurality of chip areas of a semiconductor wafer having the chip areas and boundary regions both being provided in a surface of the semiconductor wafer; forming a surface-side protective member so as to cover the surface of the semiconductor wafer and the protruded electrodes removing the semiconductor wafer corresponding to the boundary regions and forming trenches which expose the surface-side protective member; forming a back-side protective member with which the trenches are filled and which covers the back of the semiconductor wafer; and dividing the semiconductor wafer in the boundary regions with widths thinner than those of the trenches in such a manner that the surface-side protective member and the back-side protective member charged into the trenches are left in cut sections.
摘要翻译：一种制造半导体器件的方法包括：在半导体晶片的多个芯片区域上形成凸起电极，其中芯片区域和边界区域都设置在半导体晶片的表面中; 形成表面侧保护部件，以覆盖半导体晶片的表面和突出的电极去除与边界区域相对应的半导体晶片，并形成暴露表面侧保护部件的沟槽; 形成沟槽被填充并覆盖半导体晶片背面的背面保护构件; 并且在边界区域中划分半导体晶片，其宽度比沟槽的宽度薄，使得充填到沟槽中的表面侧保护构件和背面保护构件留在切割部分中。

3. 发明授权

US08996422B2 Substrate processing system, method of confirmation of its state of use, and method of prevention of illicit use 有权
标题翻译：基板加工系统，确认其使用状态的方法以及防止非法使用的方法
公开(公告)号：US08996422B2
公开(公告)日：2015-03-31
申请号：US11659878
申请日：2005-08-10
申请人： Hiroyuki Suzuki , Shinichi Okita , Tadashi Yamaguchi
发明人： Hiroyuki Suzuki , Shinichi Okita , Tadashi Yamaguchi
IPC分类号： G06F21/00 , G06Q30/06 , G03F7/20 , G06F21/71 , G06Q10/10 , H01L21/67
CPC分类号： G06Q30/06 , G03F7/70425 , G03F7/70508 , G06F21/71 , G06F2221/2105 , G06F2221/2113 , G06F2221/2137 , G06F2221/2149 , G06Q10/10 , G06Q2220/18 , H01L21/67253 , H01L21/67294
摘要： [PROBLEM] To enable confirmation of whether a substrate processing system is being illicitly used and preventing that use when there is the fact of illicit use.[MEANS FOR SOLUTION] A license file LF is a file encrypting license information L including usage terms of a substrate processing system for a specific user. A match confirmation program P2 confirms the match between the content of the license file LF decrypted by a decryption program P1 and device information DI, network information NI, and current time CT obtained from the substrate processing system to confirm the existence of the fact of illicit use. If there is illicit use, the control program P3 stops operation of the substrate processing system until predetermined action is taken based on the information from the match confirmation program P2.
摘要翻译： [问题]为了确认基板处理系统是否被非法使用，并且在存在非法使用的情况下防止使用。 [解决方案]许可证文件LF是包括用于特定用户的基板处理系统的使用条件的文件加密许可证信息L. 匹配确认程序P2确认由解密程序P1解密的许可证文件LF的内容与设备信息DI，网络信息NI和从基板处理系统获得的当前时间CT之间的匹配，以确认是否存在非法的事实使用。如果存在非法使用，则控制程序P3基于来自匹配确认程序P2的信息停止基板处理系统的操作，直到采取预定的动作为止。

4. 发明申请

US20150075840A1 HOLLOW CORE BODY FOR SIGNAL TRANSMISSION CABLE 有权
标题翻译：用于信号传输电缆的中空体
公开(公告)号：US20150075840A1
公开(公告)日：2015-03-19
申请号：US14345053
申请日：2011-10-04
申请人： Tadashi Yamaguchi , Shigehiro Sasai
发明人： Tadashi Yamaguchi , Shigehiro Sasai
IPC分类号： H01B7/04 , H01B11/00
CPC分类号： H01B7/04 , H01B11/00 , H01B11/1808 , H01B11/1856 , H01B13/0006
摘要： A hollow core body for signal transmission cable comprises an inner conductor that employs a compressed bunched conductor formed by bunching and compressing plural strands such that a cross-section of the compressed bunched conductor is substantially circular, and a hollow insulating core that includes an inner annular member, rib members, an outer annular member; and hollow members. Accordingly, as almost no recesses are produced on the circumferential surface of the compressed bunched conductor, weakening of the mechanical strength due to presence of recesses on the circumferential surface of the inner conductor can be suppressed.
摘要翻译：用于信号传输电缆的中空芯体包括内导体，其使用通过聚束和压缩多股而形成的压缩聚束导体，使得压缩的聚束导体的横截面基本上为圆形，以及中空绝缘芯，其包括内环形构件，肋构件，外环形构件; 和中空构件。因此，由于在压缩的聚束导体的圆周表面上几乎没有产生凹陷，因此可以抑制由于在内导体的圆周表面上存在凹陷而导致的机械强度的弱化。

5. 发明授权

US08796143B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08796143B2
公开(公告)日：2014-08-05
申请号：US13295050
申请日：2011-11-12
申请人： Tadashi Yamaguchi
发明人： Tadashi Yamaguchi
IPC分类号： H01L21/44
CPC分类号： H01L21/324 , H01L21/28052 , H01L21/28518 , H01L21/67103 , H01L21/67115 , H01L21/6719 , H01L21/6875 , H01L21/823814 , H01L21/823835 , H01L29/665
摘要： A semiconductor device in which a metal silicide layer is formed by a salicide process is improved in reliability. By a salicide process according to a partial reaction method, metal silicide layers are formed over respective surfaces of gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions. In a first heat treatment when the metal silicide layers are formed, a heat-conduction type anneal apparatus is used for the heat treatment of a semiconductor wafer. In a second heat treatment, a microwave anneal apparatus is used for the heat treatment of the semiconductor wafer, thereby reducing the temperature of the second heat treatment and preventing abnormal growth of the metal silicide layers. Thus, a junction leakage current in the metal silicide layers is reduced.
摘要翻译：通过自对准硅化物工艺形成金属硅化物层的半导体器件的可靠性提高。通过根据部分反应方法的自对准硅化物工艺，在栅电极，n +型半导体区域和p +型半导体区域的各个表面上形成金属硅化物层。在形成金属硅化物层的第一热处理中，使用导热型退火装置进行半导体晶片的热处理。在第二热处理中，微波退火装置用于半导体晶片的热处理，从而降低第二热处理的温度并防止金属硅化物层的异常生长。因此，金属硅化物层中的结漏电流减小。

6. 发明授权

US08541297B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08541297B2
公开(公告)日：2013-09-24
申请号：US13046761
申请日：2011-03-13
申请人： Tadashi Yamaguchi , Takuya Futase
发明人： Tadashi Yamaguchi , Takuya Futase
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/67207 , H01L21/67748 , H01L21/68735 , H01L21/68764 , H01L21/823814 , H01L21/823835 , H01L29/665
摘要： The present invention improves the performance of a semiconductor device wherein a metal silicide layer is formed through a salicide process. A metal silicide layer is formed over the surfaces of first and second gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions through a salicide process of a partial reaction type without the use of a salicide process of a whole reaction type. In a heat treatment for forming the metal silicide layer, by heat-treating a semiconductor wafer not with an annealing apparatus using lamps or lasers but with a thermal conductive annealing apparatus using carbon heaters, a thin metal silicide layer is formed with a small thermal budget and a high degree of accuracy and microcrystals of NiSi are formed in the metal silicide layer through a first heat treatment.
摘要翻译：本发明改进了通过自对准硅化物工艺形成金属硅化物层的半导体器件的性能。通过部分反应型的自对准硅化物工艺，在不使用整个反应类型的自对准硅化物工艺的情况下，在第一和第二栅电极，n +型半导体区域和p +型半导体区域的表面上形成金属硅化物层。在用于形成金属硅化物层的热处理中，通过不使用灯或激光器的退火设备对半导体晶片进行热处理，但是使用具有碳加热器的导热退火装置，以小的热预算形成薄金属硅化物层并且通过第一热处理在金属硅化物层中形成高精度的NiSi微晶。

7. 发明授权

US08343827B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08343827B2
公开(公告)日：2013-01-01
申请号：US13182750
申请日：2011-07-14
申请人： Tadashi Yamaguchi , Keiichiro Kashihara , Yoji Kawasaki
发明人： Tadashi Yamaguchi , Keiichiro Kashihara , Yoji Kawasaki
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.
摘要翻译：在CMIS器件中，为了改善通过使用应变硅技术形成的n沟道电场晶体管的工作特性，而不降低p沟道场效应晶体管的工作特性。在形成pISIS的nMIS和源极/漏极（p型延伸区域和p型扩散区域）的源极/漏极（n型延伸区域和n型扩散区域）之后，源极/漏极具有所需的浓度分布和电阻，在n型扩散区域中形成具有所需量的应变的Si：C层，因此Si：C层中的最佳寄生电阻和最佳应变量在nMIS的源/漏中获得。此外，通过在等于或短于1毫秒的短时间内形成Si：C层进行热处理，已经形成的p型延伸区域的各个p型杂质的浓度分布的变化和 p型扩散区被抑制。

8. 发明申请

US20120133787A1 IMAGING DEVICE, IMAGE PROCESSING METHOD, AND COMPUTER PROGRAM 有权
标题翻译：成像设备，图像处理方法和计算机程序
公开(公告)号：US20120133787A1
公开(公告)日：2012-05-31
申请号：US13267112
申请日：2011-10-06
申请人： Tadashi Yamaguchi
发明人： Tadashi Yamaguchi
IPC分类号： H04N5/228 , H04N5/217
CPC分类号： H04N5/23212 , H04N5/2258 , H04N5/23287 , H04N5/3696
摘要： An imaging device includes: a first imaging unit which does not include a phase difference detecting pixel on an imaging element; a second imaging unit which includes a phase difference detecting pixel on an imaging element; a pixel comparing unit which compares first obtained image obtained by the first imaging unit with a second obtained image obtained by the second imaging unit; a correcting unit which corrects phase difference information obtained by the second imaging unit based on a comparison result by the image comparing unit; a phase difference applying unit which applies the phase difference information corrected by the correcting unit to the first obtained image; and a recording unit which records image information.
摘要翻译：一种成像装置包括：第一成像单元，其不包括成像元件上的相位差检测像素; 第二成像单元，其包括成像元件上的相位差检测像素; 像素比较单元，其将由第一成像单元获得的第一获得图像与由第二成像单元获得的第二获得图像进行比较; 校正单元，其基于图像比较单元的比较结果校正由第二成像单元获得的相位差信息; 相位差施加单元，将由校正单元校正的相位差信息应用于第一获得图像; 以及记录图像信息的记录单元。

9. 发明授权

US07875539B2 Semiconductor device 有权
公开(公告)号：US07875539B2
公开(公告)日：2011-01-25
申请号：US12234079
申请日：2008-09-19
申请人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
发明人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
IPC分类号： H01L21/20
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

10. 发明申请

US20100327454A1 SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件，以及制造半导体器件的方法
公开(公告)号：US20100327454A1
公开(公告)日：2010-12-30
申请号：US12792036
申请日：2010-06-02
申请人： Tadashi Yamaguchi
发明人： Tadashi Yamaguchi
IPC分类号： H01L23/498
CPC分类号： H01L23/3192 , H01L21/561 , H01L23/3114 , H01L23/525 , H01L23/544 , H01L24/02 , H01L24/11 , H01L24/13 , H01L2223/54433 , H01L2223/54453 , H01L2224/0231 , H01L2224/0236 , H01L2224/02375 , H01L2224/0401 , H01L2224/16 , H01L2224/274 , H01L2224/27416 , H01L2924/14 , H01L2924/00
摘要： There is provided a semiconductor device including: an insulating layer provided on a substrate and formed with plural cavities; wiring lines provided on the insulating layer; plural branched wiring lines that branch from the wiring lines so as to respectively overlap with the plural cavities when seen in plan view; a conductive portion formed on the wiring lines; an external terminal formed on the conductive portion; and a sealing resin layer that seals the wiring lines and the conductive portion.
摘要翻译：提供一种半导体器件，包括：绝缘层，设置在基板上并形成有多个空腔; 设在绝缘层上的布线; 多个分支布线从布线分支，以在平面图中看到时分别与多个空腔重叠; 形成在布线上的导电部分; 形成在所述导电部上的外部端子; 以及密封树脂层，其密封布线和导电部。

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