专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5550994A Condition decision circuit for a microcomputer 失效
标题翻译：微机的状态判定电路
公开(公告)号：US5550994A
公开(公告)日：1996-08-27
申请号：US247836
申请日：1994-05-23
申请人： Tetsu Tashiro , Yoshiki Cho
发明人： Tetsu Tashiro , Yoshiki Cho
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/48 , G06F9/40
CPC分类号： G06F9/322 , G06F9/3867
摘要： A high-speed microcomputer having a condition decision circuit in which a signal output indicating whether or not a branch condition is satisfied is always active by taking out only a necessary bit by a mask register value after comparing a register value and a compare register value for every bit.
摘要翻译：一种具有状态判定电路的高速微型计算机，其中指示是否支持转移条件的信号输出总是通过在将寄存器值与比较寄存器值进行比较之后，仅通过掩码寄存器值取出必要位来激活每一点。

2. 发明授权

US5392317A Method and apparatus extracting pulse signal 失效
标题翻译：方法和设备提取脉冲信号
公开(公告)号：US5392317A
公开(公告)日：1995-02-21
申请号：US839524
申请日：1992-02-20
申请人： Yoshiki Cho , Tetsu Tashiro
发明人： Yoshiki Cho , Tetsu Tashiro
IPC分类号： H03K5/08 , H04L25/06 , H04N7/025 , H04N7/03 , H04N7/035 , H04L25/10
CPC分类号： H03K5/082 , H04L25/062
摘要： A pulse-signal extracting method and apparatus which are capable of generating an accurate pulse output even if the pulse input signal greatly pulsates due to a low-frequency noise component. A predetermined offset voltage is added to the input signal where the low-frequency noise component is superimposed on a pulse waveform which is the signal component so as to obtain an amplified signal. This amplified signal is inputted to a low-pass filter so as to output only the amplified flow-frequency component, and the original input signal is compared with the amplified low-frequency component in a comparator so as to extract the pulse waveform, which is the signal component, on the basis of the comparison result.
摘要翻译：即使脉冲输入信号由于低频噪声分量而大幅脉动，也能够产生精确的脉冲输出的脉冲信号提取方法和装置。将预定的偏移电压加到其中低频噪声分量叠加在作为信号分量的脉冲波形上以便获得放大信号的输入信号中。该放大信号被输入到低通滤波器，以仅输出放大的流频分量，并将原始输入信号与比较器中放大的低频分量进行比较，以提取脉冲波形信号分量，基于比较结果。

3. 发明授权

US5566303A Microcomputer with multiple CPU'S on a single chip with provision for testing and emulation of sub CPU's 失效
标题翻译：具有多个CPU的微型计算机在单个芯片上提供用于子CPU的测试和仿真
公开(公告)号：US5566303A
公开(公告)日：1996-10-15
申请号：US251556
申请日：1994-05-31
申请人： Tetsu Tashiro , Yoshiki Cho
发明人： Tetsu Tashiro , Yoshiki Cho
IPC分类号： G06F11/28 , G01R31/317 , G06F11/22 , G06F11/26 , G06F11/273 , G06F15/78 , G06F13/00
CPC分类号： G06F11/261 , G01R31/31701 , G06F11/2736
摘要： A control circuit is provided which enables the main CPU 23 to access a memory space of the sub CPU 1 by means of the test mode control register 4 which can be controlled via the main CPU bus 10. Also a control circuit is provided to branch into a break routine by comparing the value of the program counter 5 of the sub CPU 1 and the value set in the break vector register 7. Further, a control circuit which enables it to reset the sub CPU 1, to branch according to a test vector and to make break branch under the control of the main CPU 23 is provided, thereby making it easy to incorporate the sub CPU 1 on-chip in the conventional single CPU constitution. Thus testing environment and debugging environment for the sub CPU 1 is provided in the microcomputer having a plurality of CPUs on a single chip without connecting the exclusive test terminal of the sub CPU 1 or the sub CPU bus 28 with the outside.
摘要翻译：提供了一种控制电路，其使得主CPU 23能够通过可以经由主CPU总线10控制的测试模式控制寄存器4访问子CPU 1的存储器空间。还提供控制电路以分支到通过比较子CPU 1的程序计数器5的值和在中断向量寄存器7中设置的值的中断程序。此外，控制电路使其能够根据测试向量进行分支并且在主CPU 23的控制下进行中断分支，从而使得易于在现有的单CPU结构中并入子CPU 1。因此，在没有将副CPU 1或副CPU总线28的排他性测试终端与外部连接的情况下，在单个芯片上的具有多个CPU的微型计算机中提供子CPU1的测试环境和调试环境。

4. 发明授权

US5530906A Control circuit responses to a wait request from an address decoder for controlling clock signal supply to a CPU to operate with slow peripheral 失效
标题翻译：控制电路响应来自地址解码器的等待请求，用于控制CPU向CPU提供慢速外设的时钟信号供给
公开(公告)号：US5530906A
公开(公告)日：1996-06-25
申请号：US357564
申请日：1994-12-16
申请人： Yoshiki Cho , Shinichi Hirose
发明人： Yoshiki Cho , Shinichi Hirose
IPC分类号： G06F12/06 , G06F1/08 , G06F13/42 , G06F15/78 , G11C8/12 , G06F1/04 , G06F1/12
CPC分类号： G06F1/08 , G11C8/12
摘要： A single-chip microcomputer (5) for controlling a peripheral circuit (7) having a constant process speed regardless of its process contents, is provided with a counter (2) for counting to a predetermined count so that a frequency of the clock signal is divided by the count and used as an operation clock for controlling the peripheral circuit.
摘要翻译：用于控制与处理内容无关的具有恒定处理速度的外围电路（7）的单片微计算机（5）设置有用于计数到预定计数的计数器（2），使得时钟信号的频率为除以计数，并用作控制外围电路的操作时钟。

5. 发明授权

US06343334B1 Detector of an oscillation stopping and an apparatus for executing a treatment after the detection of an oscillation stopping 失效
标题翻译：振荡停止检测器和检测振荡停止后进行处理的装置
公开(公告)号：US06343334B1
公开(公告)日：2002-01-29
申请号：US09265384
申请日：1999-03-10
申请人： Toshiyuki Uemura , Yoshiki Cho
发明人： Toshiyuki Uemura , Yoshiki Cho
IPC分类号： G06F1314
CPC分类号： G06F1/24
摘要： A detector of an oscillation stopping, which detects the stopping of the oscillation of external clock 11, without increasing the load of CPU 45 in the micro computer 40, and generates a signal to reset the micro computer or exchanges the system clock from the external clock to an inner clock. In an embodiment, one shot pulse is generated for every standing up and/or down edge of the external clock. A capacitor of the charge-discharge circuit is charged and discharged at every one shot pulse. The voltage of the charge-discharge circuit is watched by a Schmitt circuit. When the voltage of the charge-discharge circuit exceeds a predetermined voltage, a signal for resetting the micro computer is generated. In another embodiment, an inner clock oscillation circuit, comprised of a ring oscillator, for example, is actuated, when the voltage of the charge/discharge circuit exceeds a predetermined voltage, and the system clock of the micro computer is exchanged to the inner clock from the external clock. In another embodiment, an interruption signal is sent to the CPU of the micro computer to execute an appropriate treatment after the stopping of the clock oscillation, when the voltage of the charge/discharge circuit exceeds a predetermined voltage. In another embodiment, a watchdog timer monitors the malfunction of the micro computer. It is judged whether the accident is a stopping of the oscillation of the clock or a malfunction of the micro computer. The treatment after the stopping of the clock is executed, according to the reason of the accident.
摘要翻译：振荡停止的检测器，其检测外部时钟11的振荡的停止，而不增加微型计算机40中的CPU45的负载，并产生复位微型计算机或从外部时钟交换系统时钟的信号在一个实施例中，对于外部时钟的每个站立和/或下降沿产生单次脉冲。充放电电路的电容器以每一个脉冲脉冲进行充放电。充电 - 放电电路的电压由施密特电路观察。当充放电电路的电压超过预定电压时，产生用于复位微型计算机的信号。在另一实施例中，例如由环形振荡器构成的内部时钟振荡电路被驱动，当电压充电/放电电路超过预定电压，并且微计算机的系统时钟从外部时钟交换到内部时钟。在另一个实施例中，中断信号被发送到微计算机的CPU以执行适当的处理在停止时钟振荡之后，当充电/放电电路的电压超过预定电压时。在另一实施例中，看门狗定时器监视微机的故障。判断事故是否停止时钟的振荡或微计算机的故障。根据事故原因，执行时钟停止后的处理。

6. 发明授权

US5936452A Device for detecting a plurality of signal levels indicating stopping of a clock signal 失效
标题翻译：用于检测指示停止时钟信号的多个信号电平的装置
公开(公告)号：US5936452A
公开(公告)日：1999-08-10
申请号：US735079
申请日：1996-10-18
申请人： Masayuki Utsuno , Masahiro Asano , Yoshiki Cho
发明人： Masayuki Utsuno , Masahiro Asano , Yoshiki Cho
IPC分类号： G06F11/30 , G06F1/04 , G06F1/24 , G06F11/00 , H03K3/00
CPC分类号： G06F11/076 , G06F1/24 , G06F11/0757
摘要： The oscillation-stop detecting device accurately detects the stopping of a clock signal due to various causes. The voltage detecting circuit detects when a clock signal output from the clock signal oscillator remains at a high, a low or an intermediate level, and outputs a clock voltage detection signal. The oscillation-stop detecting circuit outputs a detection signal in response to the voltage detection signal.
摘要翻译：振荡停止检测装置由于各种原因精确地检测到时钟信号的停止。电压检测电路检测从时钟信号振荡器输出的时钟信号何时保持高电平，低电平或中间电平，并输出时钟电压检测信号。振荡停止检测电路根据电压检测信号输出检测信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式