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1. 发明授权

US4450515A Bias-voltage generator 失效
标题翻译：偏压发生器
公开(公告)号：US4450515A
公开(公告)日：1984-05-22
申请号：US388194
申请日：1982-06-14
申请人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Norihisa Tsuge , Tsuyoshi Ohira
发明人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Norihisa Tsuge , Tsuyoshi Ohira
IPC分类号： H01L27/04 , G05F3/20 , G11C11/407 , H01L21/822 , H03K17/06 , H03K19/00 , H03K19/094 , H02M3/18 , H03K3/01
CPC分类号： G05F3/205
摘要： A bias-voltage generator suitable for measuring a substrate leakage current is disclosed. The bias-voltage generator comprises of an oscillator, a charge-pumping circuit which is driven by the oscillator via a pumping capacitor, and a charge-pumping switch. The charge-pumping switch is connected in series with the charge-pumping circuit. The charge-pumping switch cooperates with an external electrode for controlling the ON or OFF condition of the charge pumping circuit. The charge-pumping switch is turned OFF by the external electrode becoming a floating state and a resistor employed to ensure the charge pumping switch is inoperable after the above-mentioned measurement is completed and the circuit is shipped from the factory.
摘要翻译：公开了一种适用于测量衬底漏电流的偏置电压发生器。偏置电压发生器包括振荡器，由振荡器经由泵浦电容器驱动的电荷泵浦电路和电荷泵浦开关。电荷泵开关与充电电路串联。电荷泵开关与外部电极配合，用于控制电荷泵送电路的导通或关断状态。通过外部电极变为浮置状态，电荷泵浦开关被切断，并且在上述测量完成并且电路从工厂出货之后用于确保电荷泵开关不可操作的电阻器。

2. 发明授权

US4484312A Dynamic random access memory device 失效
标题翻译：动态随机存取存储器
公开(公告)号：US4484312A
公开(公告)日：1984-11-20
申请号：US392077
申请日：1982-06-25
申请人： Tomio Nakano , Masao Nakano , Yoshihiro Takemae , Norihisa Tsuge , Tsuyoshi Ohira
发明人： Tomio Nakano , Masao Nakano , Yoshihiro Takemae , Norihisa Tsuge , Tsuyoshi Ohira
IPC分类号： G11C11/401 , G11C11/4099 , G11C11/40
CPC分类号： G11C11/4099
摘要： A dynamic random access memory device which comprises one-transistor, one-capacitor-type memory cells (C.sub.00 .about.C.sub.127,127) in rows and columns and dummy cells (DC.sub.20 '.about.DC.sub.2,127 ', DC.sub.20 ".about.DC.sub.2,127 ", DC.sub.20 "'.about.DC.sub.2,127 "') in rows. The capacitors (C.sub.d) of the dummy cells are charged to a high power supply potential (V.sub.CC) by one or more charging transistors (Q.sub.A or Q.sub.A ') clocked by a reset clock signal (.phi..sub.R). The capacitors (C.sub.d) of the dummy cells are discharged to a low power supply potential (V.sub.SS) by one or more transistors (Q.sub.B or Q.sub.B ') clocked by an operation clock signal (.phi..sub.WL) having a potential lower than the high power supply potential (V.sub.CC).
摘要翻译：一种动态随机存取存储器件，其包括行和列中的单晶体管，单电容器型存储单元（C00 DIFFERENCE C127,127）和虚设单元（DC20'DIFFERENCE DC2,127'，DC20“DIFFERENCE DC2,127” '，DC20'''DIFFERENCE DC2,127'''）。虚拟单元的电容器（Cd）通过由复位时钟信号（phi R）计时的一个或多个充电晶体管（QA或QA'）充电到高电源电位（VCC）。虚拟单元的电容器（Cd）由一个或多个晶体管（QB或QB'）放电到低电源电位（VSS），该晶体管（QB或QB'）由具有低于高电源电位的电位的操作时钟信号（phi WL）电位（VCC）。

3. 发明授权

US4752914A Semiconductor integrated circuit with redundant circuit replacement 失效
标题翻译：半导体集成电路与冗余电路的更换
公开(公告)号：US4752914A
公开(公告)日：1988-06-21
申请号：US739159
申请日：1985-05-30
申请人： Masao Nakano , Yoshihiro Takemae , Tomio Nakano , Takeo Tatematsu , Junji Ogawa , Takashi Horii , Yasuhiro Fujii , Kimiaki Sato , Norihisa Tsuge , Itaru Tsuge , Sachie Tsuge
发明人： Masao Nakano , Yoshihiro Takemae , Tomio Nakano , Takeo Tatematsu , Junji Ogawa , Takashi Horii , Yasuhiro Fujii , Kimiaki Sato , Norihisa Tsuge , Itaru Tsuge , Sachie Tsuge
IPC分类号： G11C29/00 , G11C8/00 , G11C7/00
CPC分类号： G11C29/835
摘要： A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.
摘要翻译：一种半导体集成电路，包括存储单元，用于存储故障电路部分的地址信息，并通过冗余电路部分来替换故障电路部分。半导体集成电路提供用于检测从存储单元读取的数据与接收到的输入地址之间的一致性的比较单元。通过比较单元的比较产生的数据通过外部连接终端传送。

4. 发明授权

US4707806A Semiconductor integrated circuit device having fuse-type information storing circuit 失效
标题翻译：具有熔丝型信息存储电路的半导体集成电路装置
公开(公告)号：US4707806A
公开(公告)日：1987-11-17
申请号：US712149
申请日：1985-03-15
申请人： Yoshihiro Takemae , Tomio Nakano , Takeo Tatematsu , Junji Ogawa , Takashi Horii , Yasuhiro Fujii , Masao Nakano , Norihisa Tsuge, deceased
发明人： Yoshihiro Takemae , Tomio Nakano , Takeo Tatematsu , Junji Ogawa , Takashi Horii , Yasuhiro Fujii , Masao Nakano , Norihisa Tsuge, deceased
IPC分类号： H01L27/00 , G11C8/10 , G11C17/14 , G11C17/16 , G11C29/00 , G11C29/04 , H01L23/525 , G11C11/00
CPC分类号： G11C29/785 , G11C17/16 , G11C8/10 , H01L23/5256 , H01L2924/0002
摘要： A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse.In a normal operation, the voltage output from the voltage level conversion circuit can be set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse to which the voltage is applied, but higher than the threshold voltage of the information detection circuit.
摘要翻译：连接在第一和第二电压馈送线之间的装置包括信息存储电路，该信息存储电路具有熔丝，用于通过吹送或不熔断熔丝来存储信息;电压电平转换电路，连接到第一和第二电压馈送线中的至少一个并输出一个电压低于第一和第二电压馈送线之间的电压到信息存储电路，以及电路，连接在第一和第二电压馈送线之间，用于响应于信息存储中的熔丝处的电压值输出检测信号从电压电平转换电路向其施加电压的电路，以及哪个电压值随着保险丝的熔断或非吹出状态而变化。在正常操作中，可以将从电压电平转换电路输出的电压设置得尽可能低以抑制在施加电压的熔丝的熔断部分附近引起的电迁移，但是高于信息检测电路。

5. 发明授权

US4592025A Information storing circuit using blown and unblown fuses 失效
标题翻译：信息存储电路采用熔断和未熔丝保险丝
公开(公告)号：US4592025A
公开(公告)日：1986-05-27
申请号：US598742
申请日：1984-04-10
申请人： Yoshihiro Takemae , Junji Ogawa , Yasuhiro Fujii , Tomio Nakano , Takeo Tatematsu , Takashi Horii , Masao Nakano , Norihisa Tsuge, deceased
发明人： Yoshihiro Takemae , Junji Ogawa , Yasuhiro Fujii , Tomio Nakano , Takeo Tatematsu , Takashi Horii , Masao Nakano , Norihisa Tsuge, deceased
IPC分类号： G11C17/14 , G11C17/16 , G11C17/18 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/785 , G11C17/16 , G11C17/18
摘要： A circuit for storing information by blown and unblown fuses has at least two fuses per bit and an information output circuit. The information output circuit discriminates between the state in which all the fuses are unblown and the state in which at least one of the fuses is blown, and provides an output in accordance with the result of the discrimination as stored information.
摘要翻译：通过熔断和未熔断保险丝存储信息的电路每位具有至少两个熔丝和一个信息输出电路。信息输出电路鉴别所有保险丝未被吹出的状态和至少一个保险丝被熔断的状态，并根据鉴别结果提供输出作为存储信息。

6. 发明授权

US4970693A Semiconductor memory device with internal control signal based upon output timing 失效
标题翻译：具有基于输出定时的内部控制信号的半导体存储器件
公开(公告)号：US4970693A
公开(公告)日：1990-11-13
申请号：US484474
申请日：1990-02-23
申请人： Shigeki Nozaki , Tsuyoshi Ohira , Masaru Satoh , Tomio Nakano , Yoshihiro Takemae
发明人： Shigeki Nozaki , Tsuyoshi Ohira , Masaru Satoh , Tomio Nakano , Yoshihiro Takemae
IPC分类号： G11C11/409 , G11C7/22 , G11C8/18 , G11C11/40 , G11C11/413
CPC分类号： G11C7/22 , G11C8/18
摘要： A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.
摘要翻译：半导体存储器件连接到电源，并且包括连接以从电源接收参考电位的参考电位线。输入电路连接到参考电位线，并接收具有参考参考电位定义的逻辑电平的外部输入信号以提供给源极电位线。输出电路具有连接到参考电位线的外部输出端子。输出电路用于产生到外部输出端子的输出。禁止电路在输出电路的输出变化的预定时间段期间阻止对输入电路的外部输入信号的响应。

7. 发明授权

US4532613A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4532613A
公开(公告)日：1985-07-30
申请号：US356487
申请日：1982-03-09
申请人： Yoshihiro Takemae , Tomio Nakano , Tsuyoshi Ohira
发明人： Yoshihiro Takemae , Tomio Nakano , Tsuyoshi Ohira
IPC分类号： G11C11/407 , G11C11/409 , G11C11/4093 , G11C11/40
CPC分类号： G11C11/4093
摘要： In a semiconductor memory device including an output buffer circuit receiving data signals read out from a memory cell array, an output stage MOS transistor being turned ON and OFF according to the output signals of the output buffer circuit, and an output buffer enable (OBE) signal generator circuit for generating an OBE signal which is used as the voltage supply to the output stage of the output buffer circuit, a V.sub.BS voltage generator circuit is provided for generating a voltage V.sub.BS higher than the voltage source V.sub.CC preceding the rising up of the OBE signal, which voltage V.sub.BS is used as a voltage supply to the output stage of the OBE signal generator circuit, whereby the OBE signal is formed as a voltage waveform which rises rapidly up to a level higher than the voltage source V.sub.CC.
摘要翻译：在包括从存储单元阵列读出的数据信号的输出缓冲电路的半导体存储器件中，输出级MOS晶体管根据输出缓冲电路的输出信号而导通和截止，而输出缓冲器使能（OBE）信号发生器电路，用于产生用作向输出缓冲电路的输出级的电压供给的OBE信号，提供VBS电压发生器电路，用于产生比OBE上升之前的电压源VCC高的电压VBS 信号，哪个电压VBS被用作到OBE信号发生器电路的输出级的电压供应，由此OBE信号形成为快速上升到高于电压源VCC的电平的电压波形。

8. 发明授权

US4413272A Semiconductor devices having fuses 失效
标题翻译：具有保险丝的半导体器件
公开(公告)号：US4413272A
公开(公告)日：1983-11-01
申请号：US183734
申请日：1980-09-03
申请人： Hirohiko Mochizuki , Masao Nakano , Fumio Baba , Tomio Nakano , Yoshihiro Takemae
发明人： Hirohiko Mochizuki , Masao Nakano , Fumio Baba , Tomio Nakano , Yoshihiro Takemae
IPC分类号： G11C17/06 , G11C17/00 , G11C17/14 , G11C17/16 , H01L23/50 , H01L23/52 , H01L23/525 , H01L23/62
CPC分类号： G11C17/16 , H01L23/5256 , H01L23/62 , H01L2924/0002
摘要： A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.
摘要翻译：半导体存储器件具有涂覆有保护层的保险丝。选择性地蚀刻保护层以打开窗口，以便露出保险丝的中心部分。在中心窗口打开之后，执行保险丝的熔合操作以在熔断体的中心窗部分中打开间隙。在优选实施例中，然后添加另一保护层以填充熔断保险丝中的间隙。

9. 发明授权

US4392211A Semiconductor memory device technical field 失效
标题翻译：半导体存储器技术领域
公开(公告)号：US4392211A
公开(公告)日：1983-07-05
申请号：US243927
申请日：1981-02-20
申请人： Masao Nakano , Fumio Baba , Tomio Nakano , Yoshihiro Takemae , Hirohiko Mochizuki
发明人： Masao Nakano , Fumio Baba , Tomio Nakano , Yoshihiro Takemae , Hirohiko Mochizuki
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/844
摘要： A semiconductor memory device wherein a redundancy memory cell array incorporated with main memory cell matrixes is disclosed. Memory cells of the main memory cell matrixes are selected by first and third decoders while memory cells of the redundancy memory cell array are selected by second and third decoders. When the redundancy memory cell array is selected by the second decoder, the transmission of a clock signal to the first decoders is stopped by a switching circuit.
摘要翻译： PCT No.PCT / JP80 / 00143 Sec。 371日期：1981年2月25日 102（e）日期1981年2月20日PCT归档1980年6月24日PCT公布。出版物WO81 / 日本1981年1月8日。一种半导体存储器件，其中并入有主存储单元矩阵的冗余存储单元阵列被公开。主存储单元矩阵的存储单元由第一和第三解码器选择，而冗余存储单元阵列的存储单元由第二和第三解码器选择。当由第二解码器选择冗余存储单元阵列时，通过切换电路停止向第一解码器传输时钟信号。

10. 发明授权

US4707811A Semiconductor memory device having extended period for outputting data 失效
标题翻译：具有用于输出数据的延长周期的半导体存储器件
公开(公告)号：US4707811A
公开(公告)日：1987-11-17
申请号：US674313
申请日：1984-11-23
申请人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Kimiaki Sato
发明人： Yoshihiro Takemae , Tomio Nakano , Masao Nakano , Kimiaki Sato
IPC分类号： G11C11/401 , G11C7/10 , G11C8/00 , G11C8/04 , G11C8/18 , G11C11/409
CPC分类号： G11C8/04 , G11C7/1024 , G11C7/1033 , G11C8/18
摘要： A semiconductor memory device has an operational mode such as a nibble mode or page mode, a first address strobe signal is kept in an active state, and a second address strobe signal is successively switched between an active state and standby state, thereby enabling successive data output. Previous output data is reset once, in accordance with the switchover of the second address strobe signal to the active state while the first address strobe signal is in the active state, before outputting data, and the reset operation for outputting is also performed when both the first and second address strobe signals are switched to the standby state, so that the period in which the data is output is expanded.
摘要翻译：半导体存储器件具有诸如半字节模式或页面模式的操作模式，第一地址选通信号保持在活动状态，并且第二地址选通信号在活动状态和待机状态之间被连续切换，从而使能连续的数据输出。在输出数据之前，根据第二地址选通信号切换到激活状态的先前输出数据被复位一次，而在输出数据之前也执行用于输出的复位操作第一和第二地址选通信号被切换到待机状态，从而扩展数据输出的周期。

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