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1. 发明授权

US06503615B1 Wiping cleaner 有权
标题翻译：擦拭清洁剂
公开(公告)号：US06503615B1
公开(公告)日：2003-01-07
申请号：US09572462
申请日：2000-05-17
申请人： Takashi Horii , Masahiro Fukuyama , Akira Mizukami
发明人： Takashi Horii , Masahiro Fukuyama , Akira Mizukami
IPC分类号： B32B300
CPC分类号： B32B5/18 , A47L13/16 , B32B27/065 , B32B27/32 , B32B27/40 , B32B2250/02 , B32B2266/0285 , B32B2323/04 , B32B2323/10 , C08L61/28 , Y10T428/249981
摘要： Disclosed is a wiping cleaner comprising a porous material of an open-cell structure having a density of 5 to 50 kg/m3, a tensile strength of 0.6 to 1.6 kg/cm2, an elongation at break of 8 to 20%, and cell number of 80 to 300 cells/25 mm and having a surface wherein upon wiping, particles are peeled from the wiping surface by friction.
摘要翻译：公开了一种擦拭清洁剂，其包括密度为5至50kg / m 3，拉伸强度为0.6至1.6kg / cm 2，断裂伸长率为8至20％的开孔结构的多孔材料和细胞数目为80〜300个/ 25mm，具有表面，其中擦拭时，颗粒通过摩擦从擦拭表面上剥离。

2. 发明授权

US4807193A Semiconductor memory device with a detection circuit to detect word line potential 失效
标题翻译：具有检测电路的半导体存储器件，用于检测字线电位
公开(公告)号：US4807193A
公开(公告)日：1989-02-21
申请号：US81559
申请日：1987-02-25
申请人： Yoshihiro Takemae , Takeo Takematsu , Kimiaki Sato , Takashi Horii , Nobumi Kodama , Makoto Yanagisawa , Yasuhiro Takada
发明人： Yoshihiro Takemae , Takeo Takematsu , Kimiaki Sato , Takashi Horii , Nobumi Kodama , Makoto Yanagisawa , Yasuhiro Takada
IPC分类号： G11C11/409 , G11C7/22 , G11C8/18 , G11C11/407 , G11C7/00 , G11C8/00
CPC分类号： G11C8/18 , G11C7/22
摘要： A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.
摘要翻译：具有用于检测字线的电位的检测电路的单晶体管单电容型半导体存储器件，以确定用于驱动读出放大器的适当定时，从而提高存储器操作的速度。

3. 发明授权

US07581058B2 Non-volatile memory having multiple erase operations 有权
标题翻译：具有多次擦除操作的非易失性存储器
公开(公告)号：US07581058B2
公开(公告)日：2009-08-25
申请号：US11963913
申请日：2007-12-24
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY0至FARY3），缓冲单元（BMRY0至BMRY3）和控制单元（CNT）），控制单元可以控制外部和所述缓冲器单元以及当从所述外部分别接收到指令时，所述非易失性存储器单元和所述缓冲器单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

4. 发明授权

US4454076A Variable venturi carburetor 失效
标题翻译：可变文丘里化油器
公开(公告)号：US4454076A
公开(公告)日：1984-06-12
申请号：US454577
申请日：1982-12-30
申请人： Satomi Wada , Masanori Senda , Takashi Horii , Yozo Ota
发明人： Satomi Wada , Masanori Senda , Takashi Horii , Yozo Ota
IPC分类号： F02M7/17 , F02M9/06
CPC分类号： F02M7/17 , Y10S261/56
摘要： Disclosed herein is a variable venturi carburetor including at least one pressure controlling port provided at the lower peripheral portion of the suction piston and adapted to face to a mixing chamber defined directly downstream of the venturi portion. The pressure controlling port is located at such a position as to communicate with the suction chamber and an atmospheric pressure chamber during middle and high intake air flowing stages as the suction piston reciprocates transversely with respect to the venturi portion, and to communicate with the suction chamber and the mixing chamber during low intake air flowing stage.
摘要翻译：本文公开了一种可变文丘里化油器，其包括设置在吸入活塞的下周边部分处的至少一个压力控制口，并且适于面向直接在文氏管部分下游限定的混合室。压力控制口位于这样一个位置，当吸入活塞相对于文丘里管部分横向往复运动时，位于中空和高吸入气流阶段期间与抽吸室和大气压力室连通的位置，并与吸入室以及在低进气流动阶段的混合室。

5. 发明申请

US20070198770A1 Memory system and memory card 审中-公开
公开(公告)号：US20070198770A1
公开(公告)日：2007-08-23
申请号：US11730089
申请日：2007-03-29
申请人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
发明人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C16/32 , G06F13/1647 , G11C7/1042 , G11C7/1045 , G11C16/10 , G11C2216/14
摘要： A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

6. 发明申请

US20060023554A1 Nonvolatile memory apparatus 审中-公开
标题翻译：非易失存储器
公开(公告)号：US20060023554A1
公开(公告)日：2006-02-02
申请号：US11167588
申请日：2005-06-28
申请人： Toru Matsushita , Kenji Kozakai , Hajime Tanabe , Takashi Horii
发明人： Toru Matsushita , Kenji Kozakai , Hajime Tanabe , Takashi Horii
IPC分类号： G11C8/00
CPC分类号： G11C16/32 , G11C2216/22
摘要： A read command having designated a bank, can be inputted from outside. A read command having designated a bank can be inputted from outside while an operation for reading from a memory array to a data buffer is being performed at the bank. Further, a read command having designated a bank is inputted from outside, and a buffer read command having designated a bank is inputted from outside while an operation for reading from a memory array to a data buffer is being performed at the bank, whereby reading from the data buffer of the bank to the outside is enabled.
摘要翻译：可以从外部输入具有指定银行的读取命令。从存储器阵列向数据缓冲器读取的操作正在银行执行时，可以从外部输入指定存储体的读取命令。此外，从外部输入指定了存储体的读取命令，并且从外部输入具有指定存储区的缓冲器读取命令，同时在存储体中执行从存储器阵列读取到数据缓冲器的操作，从而从银行到外部的数据缓冲区被启用。

7. 发明申请

US20050015539A1 Memory system and memory card 有权
标题翻译：内存系统和存储卡
公开(公告)号：US20050015539A1
公开(公告)日：2005-01-20
申请号：US10500252
申请日：2002-01-09
申请人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
发明人： Takashi Horii , Keiichi Yoshida , Atsushi Nozoe
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G11C7/10 , G11C16/02 , G11C16/10
CPC分类号： G11C16/32 , G06F13/1647 , G11C7/1042 , G11C7/1045 , G11C16/10 , G11C2216/14
摘要： A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.
摘要翻译：存储器系统包括多个非易失性存储器芯片（CHP1和CHP2），每个非易失性存储器芯片具有可以执行彼此独立的存储器操作的多个存储器组（BNK1和BNK2）和可以控制访问每个存储器的所述非易失性存储器芯片。存储器控制器可以选择性地指示在非易失性存储器芯片的多个存储体上的同时写入操作或交错写入操作。因此，在同时写入操作中，可以完全并行地执行比写入建立时间长得多的写入操作。在交错写入操作中，可以执行写入设置之后的写入操作，以便部分地与另一个存储体上的写入操作重叠。结果，可以使构成高速写入操作的存储器系统的非易失性存储器芯片的数量相对较小。

8. 发明授权

US5440511A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5440511A
公开(公告)日：1995-08-08
申请号：US210385
申请日：1994-03-18
申请人： Hiroshi Yamamoto , Kiyonori Ogura , Takashi Horii
发明人： Hiroshi Yamamoto , Kiyonori Ogura , Takashi Horii
IPC分类号： H03K5/1252 , G11C8/18 , G11C11/409 , H03K19/003 , G11C7/00
CPC分类号： G11C8/18
摘要： A semiconductor memory device has a first control signal is externally input to an input buffer circuit. A second control signal output from the input buffer circuit is input to an internal circuit. The internal circuit comprises a memory cell array having a number of memory cells and peripheral circuits for writing and reading cell information in and from the memory cells, and the writing and reading operations are executed based on the second control signal. Read data output from the internal circuit is input to an output buffer, which outputs the read data as output data. Power from a common power supply is supplied to the input buffer circuit and the output buffer. A noise-remove signal generator, which is connected to the input buffer circuit, functions based on either one of the first control signal and the second control signal to generate a noise remove signal in synchronism with an output timing of the output data. A noise removing circuit removes noise from the second control signal based on the noise remove signal.
摘要翻译：半导体存储器件具有外部输入到输入缓冲器电路的第一控制信号。从输入缓冲电路输出的第二控制信号输入到内部电路。内部电路包括具有多个存储单元的存储单元阵列和用于在存储单元中写入和读取单元信息的外围电路，并且基于第二控制信号执行写入和读取操作。从内部电路输出的读取数据输入到输出缓冲器，输出读出的数据作为输出数据。来自公共电源的电源被提供给输入缓冲器电路和输出缓冲器。连接到输入缓冲器电路的噪声消除信号发生器基于第一控制信号和第二控制信号中的任一个起作用，以与输出数据的输出定时同步地产生噪声去除信号。噪声去除电路基于噪声消除信号从第二控制信号中去除噪声。

9. 发明授权

US4592025A Information storing circuit using blown and unblown fuses 失效
标题翻译：信息存储电路采用熔断和未熔丝保险丝
公开(公告)号：US4592025A
公开(公告)日：1986-05-27
申请号：US598742
申请日：1984-04-10
申请人： Yoshihiro Takemae , Junji Ogawa , Yasuhiro Fujii , Tomio Nakano , Takeo Tatematsu , Takashi Horii , Masao Nakano , Norihisa Tsuge, deceased
发明人： Yoshihiro Takemae , Junji Ogawa , Yasuhiro Fujii , Tomio Nakano , Takeo Tatematsu , Takashi Horii , Masao Nakano , Norihisa Tsuge, deceased
IPC分类号： G11C17/14 , G11C17/16 , G11C17/18 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/785 , G11C17/16 , G11C17/18
摘要： A circuit for storing information by blown and unblown fuses has at least two fuses per bit and an information output circuit. The information output circuit discriminates between the state in which all the fuses are unblown and the state in which at least one of the fuses is blown, and provides an output in accordance with the result of the discrimination as stored information.
摘要翻译：通过熔断和未熔断保险丝存储信息的电路每位具有至少两个熔丝和一个信息输出电路。信息输出电路鉴别所有保险丝未被吹出的状态和至少一个保险丝被熔断的状态，并根据鉴别结果提供输出作为存储信息。

10. 发明授权

US07334080B2 Nonvolatile memory with independent access capability to associated buffer 有权
标题翻译：非易失性存储器，具有对相关缓冲区的独立访问能力
公开(公告)号：US07334080B2
公开(公告)日：2008-02-19
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

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