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1. 发明授权

US06191902B1 Magnetic disk apparatus and magnetic disk medium 失效
标题翻译：磁盘装置和磁盘介质
公开(公告)号：US06191902B1
公开(公告)日：2001-02-20
申请号：US08925007
申请日：1997-08-27
申请人： Yoshihiro Hashimura , Shuichi Hashimoto
发明人： Yoshihiro Hashimura , Shuichi Hashimoto
IPC分类号： G11B509
CPC分类号： G11B20/10055 , G11B5/012 , G11B20/1217 , G11B20/1833 , G11B27/3027 , G11B2020/1284 , G11B2220/20
摘要： A writing unit divides a sync byte into two sync bytes of a first sync byte and a second sync byte and also divides write data into two data of first data and second data and writes them. When a first sync byte pattern is detected, a reading unit demodulates the subsequent first data, second data, and an error detection correction code. When the first sync byte pattern SB1 is not detected but a second sync byte pattern SB2 is detected, the subsequent second data and error detection correction code are demodulated and the first data is reconstructed by the error detection correction code.
摘要翻译：写入单元将同步字节划分为第一同步字节和第二同步字节的两个同步字节，并且还将写入数据划分为第一数据和第二数据的两个数据并将其写入。当检测到第一同步字节模式时，读取单元解调随后的第一数据，第二数据和错误检测校正码。当未检测到第一同步字节模式SB1而检测到第二同步字节模式SB2时，后续的第二数据和错误检测校正码被解调，并且第一数据被错误检测校正码重构。

2. 发明授权

US6147826A Magnetic disk apparatus having duplicate sync byte patterns 失效
标题翻译：具有重复的同步字节模式的磁盘装置
公开(公告)号：US6147826A
公开(公告)日：2000-11-14
申请号：US920854
申请日：1997-08-29
申请人： Yoshihiro Hashimura
发明人： Yoshihiro Hashimura
IPC分类号： G11B20/10 , G11B5/012 , G11B5/09 , G11B20/12 , G11B20/18
CPC分类号： G11B20/10055 , G11B20/1217 , G11B20/1813 , G11B20/182 , G11B5/012 , G11B5/09 , G11B2020/1222 , G11B2020/1277 , G11B2020/1287 , G11B2020/148 , G11B2220/2516
摘要： A writing unit writes a first sync byte pattern SB1 to the head of data and writes a second sync byte pattern SB2 to the end of the data (DATA+ECC). When the first sync byte pattern SB1 is not detected, the data is stored into a memory, and after that, a reading unit reads out the second sync byte pattern SB2 in the memory. When the second sync byte pattern SB2 is detected, the reading unit reads out the data of a predetermined length DL in which a position that is preceding to the detecting position by only a predetermined data length (DL) is set to the head position from the memory and demodulates.
摘要翻译：写入单元将第一同步字节模式SB1写入数据的头部，并将第二同步字节模式SB2写入数据的结尾（DATA + ECC）。当未检测到第一同步字节模式SB1时，数据被存储到存储器中，之后读取单元读出存储器中的第二同步字节模式SB2。当检测到第二同步字节图形SB2时，读取单元读出预定长度DL的数据，其中仅将预定数据长度（DL）的检测位置之前的位置设置为从头部位置存储和解调。

3. 发明授权

US6002538A PRML regenerating apparatus having adjusted slice levels 失效
标题翻译： PRML再生装置具有调整的切片水平
公开(公告)号：US6002538A
公开(公告)日：1999-12-14
申请号：US400720
申请日：1995-03-08
申请人： Masahide Kanegae , Katutoshi Asai , Yoshihiro Hashimura , Hideki Ohmori , Masahito Iwatsubo , Masao Kondou , Tomoki Sugaya , Hiroyuki Tanaka
发明人： Masahide Kanegae , Katutoshi Asai , Yoshihiro Hashimura , Hideki Ohmori , Masahito Iwatsubo , Masao Kondou , Tomoki Sugaya , Hiroyuki Tanaka
IPC分类号： G11B5/00 , G11B20/10 , G11B20/14 , G11B27/30 , H04L7/033 , H04L7/04 , H04L25/06 , G11B5/09
CPC分类号： G11B27/3027 , G11B20/10009 , G11B20/1488 , H04L25/061 , G11B2005/0018 , H04L7/041 , H04L7/044
摘要： Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level. The ternary determination circuit can be thereby actualized with a simple configuration.
摘要翻译：公开了一种用于从存储介质再生由头读取的信号的PRML再生装置。该PRML再生装置具有用于使读取信号波形均衡的波形均衡电路，用于最大似然解码的最大似然解码器，在通过将均衡输出与上限和下限电平进行比较而获得确定值之后，该确定值和控制电路，用于设定最大似然解码器的上限位电平和下限电平之间的距离。因此，可以根据均衡特性将上限和下限电平之间的距离设置为可变的。最大似然解码器的三元确定电路由用于存储均衡输出和上限或下限电平的对应表与存储器相关的确定结果和下一个上限或下限电平构成。因此可以用简单的结构实现三元确定电路。

4. 发明授权

US5696793A Phase difference detection circuit for extended partial-response class-4 signaling system 失效
标题翻译：扩展部分响应类4信令系统的相位差检测电路
公开(公告)号：US5696793A
公开(公告)日：1997-12-09
申请号：US530863
申请日：1995-09-19
申请人： Yoshihiro Hashimura
发明人： Yoshihiro Hashimura
IPC分类号： G11B20/10 , G11B20/14 , H03L7/085 , H04L7/02 , H04L7/033 , H04L25/49 , H04L25/497
CPC分类号： H04L7/0062 , G11B20/1403 , H04L25/4919 , H04L25/497 , H04L7/0334 , G11B20/10009
摘要： Disclosed is a phase difference detection circuit for detecting a phase difference between an equalized signal obtained by equalizing an extended partial-response class-4 signal and a sampling clock. This phase difference detection circuit has a sample hold circuit for sampling and holding the equalized signal at the sampling clock, a comparator circuit for comparing the sampled and held signals with at least four slice levels and converting them into determination level signals having at least quinary values and a phase difference generation circuit for generating a phase difference on the basis of at least the quinary determination level signals from the comparator circuit and outputs of the sample hold circuit. The EPR-4 signals are quinary-determined, and it is therefore possible to measure the phase difference by accurately detecting a peak position or a zero cross position of the signal.
摘要翻译：公开了一种相位差检测电路，用于检测通过均衡扩展部分响应类别-4信号和采样时钟获得的均衡信号之间的相位差。该相位差检测电路具有用于采样和保持采样时钟的均衡信号的采样保持电路，用于将采样和保持的信号与至少四个限幅电平进行比较的比较电路，并将其转换为具有至少五次值的确定电平信号以及相位差发生电路，用于至少基于来自比较器电路的四次判定电平信号和采样保持电路的输出来产生相位差。 EPR-4信号是被定义的，因此可以通过精确地检测信号的峰值位置或零交叉位置来测量相位差。

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