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1. 发明授权

US5333505A Semiconductor pressure sensor for use at high temperature and pressure and method of manufacturing same 失效
标题翻译：用于高温和高压的半导体压力传感器及其制造方法
公开(公告)号：US5333505A
公开(公告)日：1994-08-02
申请号：US3437
申请日：1993-01-12
申请人： Yoshiharu Takahashi , Tetsuya Hirose , Hiroshi Otani , Seiji Takemura
发明人： Yoshiharu Takahashi , Tetsuya Hirose , Hiroshi Otani , Seiji Takemura
IPC分类号： G01L9/00 , G01L9/06 , G01L9/08
CPC分类号： G01L19/0084 , G01L19/147 , H01L2224/48091 , H01L2224/48247 , H01L2924/10155 , H01L2924/1815 , Y10T29/49103
摘要： In a semiconductor pressure sensor, a dam which prevents a sheathing resin from flowing into a diaphragm portion during the molding of the sheathing resin is disposed on the outer periphery of piezoresistors and the diaphragm portion on the surface of a semiconductor pressure sensor chip. The volume of the base and that of the semiconductor pressure sensor chip are adjusted so that a tensile force exerted upon the semiconductor pressure sensor chip by the base cancels a compressive force exerted upon the semiconductor pressure sensor by the sheathing resin when the temperature of the semiconductor pressure sensor returns to an ordinary room temperature from a high temperature. As a result, strain is not caused in the semiconductor pressure sensor chip, and therefore measurements of pressure with a high degree of accuracy can be performed.
摘要翻译：在半导体压力传感器中，在压电电阻器的外周和半导体压力传感器芯片的表面上的隔膜部分设置防止护套树脂在护套树脂成型期间流入隔膜部分的堤坝。调整基座的体积和半导体压力传感器芯片的体积，使得由基座施加到半导体压力传感器芯片上的张力在半导体器件的温度下抵消由护套树脂施加在半导体压力传感器上的压缩力压力传感器从高温回到普通室温。结果，在半导体压力传感器芯片中不会引起应变，因此能够高精度地测量压力。

2. 发明授权

US5207102A Semiconductor pressure sensor 失效
标题翻译：半导体压力传感器
公开(公告)号：US5207102A
公开(公告)日：1993-05-04
申请号：US763217
申请日：1991-09-20
申请人： Yoshiharu Takahashi , Tetsuya Hirose , Hideyuki Ichiyama
发明人： Yoshiharu Takahashi , Tetsuya Hirose , Hideyuki Ichiyama
IPC分类号： G01L9/04 , G01L9/00 , H01L23/28 , H01L29/84
CPC分类号： G01L19/141 , G01L19/0084 , G01L19/147 , H01L2224/32245 , H01L2224/48247 , H01L2224/48465 , H01L2924/10253 , H01L2924/1815 , Y10T29/49103
摘要： A semiconductor pressure sensor is manufactured by integrally encapsulating a semiconductor pressure, sensor chip, a pedestal, leads, wires and a die pad in an outer package except for the surface of a diaphragm of the semiconductor pressure sensor chip and the reverse side of the die pad. The ratio of the thickness of the pedestal to the thickness of the semiconductor pressure sensor chip is 7.5 or less, while the ratio of the diameter of an opening formed in the outer package at the surface of the diaphragm and the diameter of the diaphragm is 1 or more. The thermal stress generated in the semiconductor pressure sensor chip can freely be reduced to a desired value, and a semiconductor pressure sensor exhibiting a desired accuracy can therefore be obtained. Furthermore, since the semiconductor pressure sensor can be manufactured by an ordinary IC manufacturing process, a semiconductor pressure sensor with reduced cost and having high quality can be produced.
摘要翻译：半导体压力传感器是通过将半导体压力传感器芯片，基座，引线，导线和芯片焊盘整体地封装在除了半导体压力传感器芯片的隔膜的表面和模具的反面之外的外部封装中来制造的垫。基座的厚度与半导体压力传感器芯片的厚度的比率为7.5以下，而在隔膜的表面形成的外部开口的直径和隔膜的直径的比率为1 或者更多。在半导体压力传感器芯片中产生的热应力可以自由地降低到期望值，因此可以获得呈现期望精度的半导体压力传感器。此外，由于可以通过普通的IC制造工艺制造半导体压力传感器，所以可以制造成本低且质量好的半导体压力传感器。

3. 发明授权

US08771602B2 Resin production apparatus and resin production method 失效
标题翻译：树脂生产设备和树脂生产方法
公开(公告)号：US08771602B2
公开(公告)日：2014-07-08
申请号：US12946382
申请日：2010-11-15
申请人： Shuzo Fujiwara , Yasuhide Suzuki , Yasuhiko Okuda , Tetsuya Hirose
发明人： Shuzo Fujiwara , Yasuhide Suzuki , Yasuhiko Okuda , Tetsuya Hirose
IPC分类号： B01J19/00 , B01J4/00
CPC分类号： B01J10/005 , B01F7/00208 , B01F7/161 , B01F7/18 , B01J4/007 , B01J19/0013 , B01J19/002 , B01J19/0066 , B01J19/18 , B01J2204/005 , B01J2219/00094 , B01J2219/00254 , B01J2219/00779 , C09J133/06
摘要： A resin production apparatus of the present invention includes: a reactor vessel having a vessel main body which polymerizes an ingredient to produce a thermoplastic synthetic resin which solidifies at room temperature and storing the synthetic resin in the molten state, an output mechanism disposed at a bottom part of the vessel main body, which outputs the synthetic resin in the molten state, and a temperature adjustment mechanism which adjusts temperatures of the vessel main body and the output mechanism so as to maintain the molten state of the synthetic resin; a cooling mechanism arranged below the reactor vessel, which continuously cools and solidifies the synthetic resin output from the output mechanism; and a crushing mechanism which crushes the synthetic resin fed out from the cooling mechanism.
摘要翻译：本发明的树脂制造装置包括：反应容器，其具有容器主体，聚合成分以制备在室温下固化并将合成树脂储存在熔融状态的热塑性合成树脂，输出机构设置在底部输出熔融状态的合成树脂的容器主体的一部分，以及调节容器主体和输出机构的温度以保持合成树脂的熔融状态的温度调节机构; 布置在反应器下方的冷却机构，其连续地冷却并固化从输出机构输出的合成树脂; 以及粉碎从冷却机构送出的合成树脂的破碎机构。

4. 发明授权

US08692623B2 Relaxation oscillator circuit including two clock generator subcircuits having same configuration operating alternately 失效
标题翻译：松弛振荡器电路包括具有相同配置的两个时钟发生器子电路
公开(公告)号：US08692623B2
公开(公告)日：2014-04-08
申请号：US13591340
申请日：2012-08-22
申请人： Seichiro Shiga , Tetsuya Hirose , Yuji Osaki
发明人： Seichiro Shiga , Tetsuya Hirose , Yuji Osaki
IPC分类号： H03K3/0231
CPC分类号： H03K3/354 , H03K3/011 , H03K5/1515
摘要： A control circuit controls first and second clock generator subcircuits so that one subcircuit of the first and second clock generator subcircuits operates for a comparison voltage generating interval, then another subcircuit operates for a clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the comparison voltage generating interval and the clock generating interval. For the comparison voltage generating interval, each of the first and second clock generator subcircuits is controlled to generate a comparison voltage and output the same voltage to an inverted output terminal of a comparator. For the clock generating interval, each of the first and second clock generator subcircuits compares an output voltage from a current-voltage converter circuit with the comparison voltage.
摘要翻译：控制电路控制第一和第二时钟发生器子电路，使得第一和第二时钟发生器子电路的一个子电路用于比较电压产生间隔，然后另一个子电路用于时钟产生间隔，并且使得第一和第二时钟发生器子电路交替地重复比较电压产生间隔和时钟产生间隔的处理。对于比较电压产生间隔，控制第一和第二时钟发生器子电路中的每一个以产生比较电压并将相同的电压输出到比较器的反相输出端。对于时钟产生间隔，第一和第二时钟发生器子电路中的每一个将电流 - 电压转换器电路的输出电压与比较电压进行比较。

5. 发明申请

US20090174051A1 Semiconductor package and semiconductor device 审中-公开
标题翻译：半导体封装和半导体器件
公开(公告)号：US20090174051A1
公开(公告)日：2009-07-09
申请号：US10585092
申请日：2005-01-12
申请人： Shuichi Osaka , Hitoshi Fujimoto , Tetsuya Hirose , Naoyuki Shinonaga
发明人： Shuichi Osaka , Hitoshi Fujimoto , Tetsuya Hirose , Naoyuki Shinonaga
IPC分类号： H01L25/04 , H01L23/48
CPC分类号： H01L25/03 , H01L23/3121 , H01L23/3135 , H01L23/4334 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/4917 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package structure which aims at improvement in function, miniaturization, and systematization of a semiconductor integrated circuit having been made into multichip is offered.A substrate in which a plurality of terminals for a test and a plurality of terminals for external connection are arranged on the front surface, and a plurality of terminals for internal connection are arranged on the back surface, and a semiconductor chip in which a plurality of surface terminals connected to an internal circuit are formed in the front surface are prepared. An encapsulated semiconductor package is formed by joining the back surface of this semiconductor chip to the back surface of the substrate, connecting the surface terminal of the semiconductor chip to the desired terminal for internal connection of the substrate, and sealing the semiconductor chip on the back surface of the substrate with a molded member. A multichip structure is made by joining the encapsulated semiconductor package to another semiconductor chip mounted on the substrate formed external connection terminals and sealing them.
摘要翻译：提供了一种旨在改进已经制成多芯片的半导体集成电路的功能，小型化和系统化的封装结构。在前表面上配置有用于测试的多个端子和用于外部连接的多个端子的基板，并且在背面上布置有用于内部连接的多个端子，并且其中多个在前表面形成连接到内部电路的表面端子。通过将该半导体芯片的背面接合到基板的背面而形成封装的半导体封装，将半导体芯片的表面端子连接到用于衬底的内部连接的期望端子，并将半导体芯片密封在背面具有模制构件的基板的表面。通过将封装的半导体封装连接到安装在形成于基板上的外部连接端子上的另一个半导体芯片并将其密封来制造多芯片结构。

6. 发明授权

US5136123A Multilayer circuit board 失效
标题翻译：多层电路板
公开(公告)号：US5136123A
公开(公告)日：1992-08-04
申请号：US172256
申请日：1988-03-23
申请人： Satoru Kobayashi , Masahiro Suzuki , Satoshi Tanaka , Tetsuya Hirose
发明人： Satoru Kobayashi , Masahiro Suzuki , Satoshi Tanaka , Tetsuya Hirose
IPC分类号： H05K1/02 , H05K1/03 , H05K3/46
CPC分类号： H05K3/4688 , H05K1/024 , H05K1/034 , H05K1/0271 , H05K2201/0116 , H05K2201/015 , H05K2201/0154 , H05K2201/09309 , H05K3/4611
摘要： A multilayer circuit board is provided having an inner porous fluororesin layer containing electrical circuits, a ground conductor layer located adjacent the fluororesin layer on one side thereof and a power supply conductor layer located adjacent the fluororesin layer on the other side thereof, and a reinforcing, solid plastic dielectric layer adjacent each conductor layer and being external to the inner fluororesin layer. In an alternate embodiment, the multilayer circuit board may have a plurality of inner porous fluororesin layers, at least one fluororesin layer containing electrical circuits, and may have ground conductors and power supply conductors adjacent each fluororesin layer, and reinforcing, solid plastic dielectric layers on the outermost surfaces of the circuit board assembly. The ground and power supply conductor layers extend over the entire surfaces, respectively, of the inner fluororesin layers.

7. 发明授权

US08421435B2 Power supply voltage controlling circuit for use in subthreshold digital CMOS circuit including minute current generator and controlled output voltage generator circuit 有权
标题翻译：用于亚阈值数字CMOS电路的电源电压控制电路，包括微电流发生器和受控输出电压发生器电路
公开(公告)号：US08421435B2
公开(公告)日：2013-04-16
申请号：US12713372
申请日：2010-02-26
申请人： Tetsuya Hirose , Yuji Osaki , Kei Matsumoto
发明人： Tetsuya Hirose , Yuji Osaki , Kei Matsumoto
IPC分类号： G05F3/16
CPC分类号： G05F3/242
摘要： In a circuit and method for correcting a delay variation of a subthreshold CMOS circuit operating in a subthreshold region, a power supply voltage controlling circuit is provided for supplying a controlled output voltage to a subthreshold digital CMOS circuit as a controlled power supply voltage. The subthreshold digital CMOS circuit includes CMOS circuits each having a pMOSFET and an nMOSFET and operating in a subthreshold region with a predetermined delay time, and further includes a minute current generator circuit generating a predetermined minute current based on a power supply voltage, and a controlled output voltage generator circuit generating a controlled output voltage for correcting a variation in the delay time based on a generated minute current and supplying the controlled output voltage to the subthreshold digital CMOS circuit as a controlled power supply voltage including a change in each threshold voltage of the pMOSFET and the nMOSFET.
摘要翻译：在用于校正在亚阈值区域中工作的亚阈值CMOS电路的延迟变化的电路和方法中，提供电源电压控制电路，用于将受控输出电压作为受控电源电压提供给次阈值数字CMOS电路。亚阈值数字CMOS电路包括各自具有pMOSFET和nMOSFET并且在具有预定延迟时间的亚阈值区域中操作的CMOS电路，并且还包括基于电源电压产生预定微小电流的微小电流发生器电路，以及受控输出电压发生器电路产生受控的输出电压，用于基于产生的微小电流来校正延迟时间的变化，并将受控输出电压提供给次阈值数字CMOS电路作为受控电源电压，该受控电源电压包括每个阈值电压的变化 pMOSFET和nMOSFET。

8. 发明申请

US20130049875A1 RELAXATION OSCILLATOR CIRCUIT INCLUDING TWO CLOCK GENERATOR SUBCIRCUITS HAVING SAME CONFIGURATION OPERATING ALTERNATELY 失效
标题翻译：松动振荡器电路，包括具有相同配置的两个时钟发生器辅助电路
公开(公告)号：US20130049875A1
公开(公告)日：2013-02-28
申请号：US13591340
申请日：2012-08-22
申请人： Seichiro SHIGA , Tetsuya Hirose , Yuji Osaki
发明人： Seichiro SHIGA , Tetsuya Hirose , Yuji Osaki
IPC分类号： H03K3/02
CPC分类号： H03K3/354 , H03K3/011 , H03K5/1515
摘要： A control circuit controls first and second clock generator subcircuits so that one subcircuit of the first and second clock generator subcircuits operates for a comparison voltage generating interval, then another subcircuit operates for a clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the comparison voltage generating interval and the clock generating interval. For the comparison voltage generating interval, each of the first and second clock generator subcircuits is controlled to generate a comparison voltage and output the same voltage to an inverted output terminal of a comparator. For the clock generating interval, each of the first and second clock generator subcircuits compares an output voltage from a current-voltage converter circuit with the comparison voltage.
摘要翻译：控制电路控制第一和第二时钟发生器子电路，使得第一和第二时钟发生器子电路的一个子电路用于比较电压产生间隔，然后另一个子电路用于时钟产生间隔，并且使得第一和第二时钟发生器子电路交替重复比较电压产生间隔和时钟产生间隔的处理。对于比较电压产生间隔，控制第一和第二时钟发生器子电路中的每一个以产生比较电压并将相同的电压输出到比较器的反相输出端。对于时钟产生间隔，第一和第二时钟发生器子电路中的每一个将电流 - 电压转换器电路的输出电压与比较电压进行比较。

9. 发明申请

US20110076481A1 ACRYLIC PRESSURE-SENSITIVE ADHESIVE TAPE OR SHEET 审中-公开
标题翻译：丙烯酸压敏胶带或薄片
公开(公告)号：US20110076481A1
公开(公告)日：2011-03-31
申请号：US12736924
申请日：2009-05-20
申请人： Tetsuya Hirose , Shinji Inokuchi , Akiko Nonaka
发明人： Tetsuya Hirose , Shinji Inokuchi , Akiko Nonaka
IPC分类号： C09J7/02 , B32B3/26
CPC分类号： C09J133/08 , C08K3/013 , C08K3/36 , C08K7/28 , C09J7/10 , C09J7/385 , C09J2201/606 , C09J2205/102 , C09J2205/11 , C09J2400/24 , C09J2433/00 , Y10T428/249974 , Y10T428/249983
摘要： Provided is an acrylic pressure-sensitive adhesive tape or sheet having high initial low-temperature adhesive strength.The acrylic pressure-sensitive adhesive tape or sheet according to the present invention is characterized by having a bubble-mixed inorganic filler-containing acrylic pressure-sensitive adhesive layer containing an acrylic polymer formed from an acrylic monomer mixture containing an alkyl (meth)acrylate ester (a) having an alkyl group having a carbon number of 1 to 14 and a polar group-containing vinyl monomer (b) at a component rate [(a)/(b)] (by weight) of 95/5 to 91/9, an inorganic filler in the amount at a rate of 0.1 parts by weight or more and less than 2 parts by weight with respect to 100 parts by weight of the all monomer components forming the acrylic polymer and bubbles.
摘要翻译：提供具有高初始低温粘合强度的丙烯酸类压敏粘合带或片材。根据本发明的丙烯酸类压敏粘合带或片材的特征在于，含有气泡混合的含无机填料的丙烯酸类压敏粘合剂层，其含有由含有（甲基）丙烯酸烷基酯的丙烯酸单体混合物形成的丙烯酸聚合物（a）具有碳数为1至14的烷基和含极性基团的乙烯基单体（b）的组分速率[（a）/（b）]（重量）为95/5至91 / 9，相对于100重量份形成丙烯酸聚合物的全部单体成分和气泡，其量为0.1重量份以上且小于2重量份的无机填料。

10. 发明授权

US06660789B2 Polyester resin composition and molding product thereof 有权
标题翻译：聚酯树脂组合物及其成型产品
公开(公告)号：US06660789B2
公开(公告)日：2003-12-09
申请号：US10101691
申请日：2002-03-21
申请人： Tomoyuki Uno , Takashi Sugata , Akira Hirai , Tetsuya Hirose , Hiroyuki Yamazaki , Kazuo Kato
发明人： Tomoyuki Uno , Takashi Sugata , Akira Hirai , Tetsuya Hirose , Hiroyuki Yamazaki , Kazuo Kato
IPC分类号： C08L6702
CPC分类号： C08L67/02 , C08L23/08 , C08L69/00 , C08L83/04 , C08L2666/02
摘要： A polyester composition comprising (A) 30 to 95 parts by weight of a polybutylene terephthalate resin containing a polybutylene terephthalate-isophthalate copolymer in which the content of an isophthalic acid ingredient to the entire dicarboxylic acid ingredient is 5 to 20 mol %, (B) 1 to 30 parts by weight of a polycarbonate resin, (C) 3 to 20 parts by weight of an elastomer and (D) 15 to 30 parts by weight of a fibrous reinforcing material, and (E) 0.1 to 3 parts by weight of a silicone compound, wherein the total amount for (A)-(D) is 100 parts by weight, the composition being used for insert molding.
摘要翻译：一种聚酯组合物，其包含（A）30〜95重量份的含有聚对苯二甲酸丁二醇酯 - 间苯二甲酸酯共聚物的聚对苯二甲酸丁二醇酯树脂，其中间苯二甲酸成分对二羧酸成分总量为5〜20摩尔％，（B） 1〜30重量份的聚碳酸酯树脂，（C）3〜20重量份的弹性体和（D）15〜30重量份的纤维增强材料，（E）0.1〜3重量份的一种硅氧烷化合物，其中（A） - （D）的总量为100重量份，该组合物用于嵌入成型。

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