专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07827551B2 Real-time threading service for partitioned multiprocessor systems 有权
标题翻译：分区多处理器系统的实时线程服务
公开(公告)号：US07827551B2
公开(公告)日：2010-11-02
申请号：US11231697
申请日：2005-09-21
申请人： Yoram Kulbak , Doron Shamia , Jimmy Scott Raynor , James P. Held , Ron Gabor
发明人： Yoram Kulbak , Doron Shamia , Jimmy Scott Raynor , James P. Held , Ron Gabor
IPC分类号： G06F9/46 , H04L9/32
CPC分类号： G06F9/4843
摘要： An embodiment of the present invention is a technique to provide a real-time threading service to an application in a multi-core environment. An executive is launched, within a most privilege level of an operating system (OS), on a real-time core in the multi-core environment. The real-time core is sequestered from the OS. A real-time thread is created in a least privilege level on the real-time core for an application using a library. The library is loaded by the application. The real-time thread shares a virtual address space with the application.
摘要翻译：本发明的实施例是一种向多核环境中的应用提供实时线程服务的技术。在多核环境中的实时核心上，一个执行者在操作系统（OS）的最高级别内启动。实时核心是从操作系统中隔离出来的。在使用库的应用程序的实时内核的最小权限级别中创建实时线程。该库由应用程序加载。实时线程与应用程序共享虚拟地址空间。

2. 发明授权

US09015455B2 Processsor integral technologies for BIOS flash attack protection and notification 有权
标题翻译：用于BIOS闪存攻击保护和通知的进程集成技术
公开(公告)号：US09015455B2
公开(公告)日：2015-04-21
申请号：US13178338
申请日：2011-07-07
申请人： James P. Held , Scott H. Robinson , Vincent J. Zimmer
发明人： James P. Held , Scott H. Robinson , Vincent J. Zimmer
IPC分类号： G06F9/00 , G06F21/57 , G06F9/44
CPC分类号： G06F21/575 , G06F9/4401 , G06F21/64
摘要： A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.
摘要翻译：用于BIOS闪存防护和通知的系统和方法。包括初始化固件验证模块的处理器初始化模块可以被配置为响应于电源接通和/或复位而首先执行并且验证处理器封装中存储在非易失性存储器中的初始化固件。初始化固件配置为验证BIOS。如果初始化固件和/或BIOS的验证失败，则系统被配置为选择多个响应中的至少一个，包括但不限于防止BIOS执行，启动恢复，报告验证失败，停止，关闭和/或允许BIOS执行，以及操作系统（OS）以有限的功能模式进行引导。

3. 发明授权

US5889988A Debugger for debugging tasks in an operating system virtual device driver 失效
标题翻译：用于在操作系统虚拟设备驱动程序中调试任务的调试器
公开(公告)号：US5889988A
公开(公告)日：1999-03-30
申请号：US748551
申请日：1996-11-08
申请人： James P. Held
发明人： James P. Held
IPC分类号： G06F9/48 , G06F11/36 , G06F9/00
CPC分类号： G06F9/4843 , G06F11/3664
摘要： A debugger that is multi-task aware and capable of providing symbolic support to a graphical user interface (GUI) is disclosed. The debugger disclosed communicates with a multi-tasking kernel nested within a driver of the operating system within the 0 privilege level. The multi-tasking kernel distinguishes among the rest of its environment where a graphical user interface executes the driver tasks being debugged. The multi-tasking kernel, in cooperation with the debugger runs each element on a different thread of the same machine, thereby allowing the debugger and the driver tasks being debugged to continue to run without stopping operation of either the graphical user interface or the operating system associated with the graphical user interface.
摘要翻译：公开了一种多任务感知并能够向图形用户界面（GUI）提供符号支持的调试器。所公开的调试器与嵌套在0特权级别内的操作系统的驱动程序内的多任务内核通信。多任务内核区分其余的环境，其中图形用户界面执行被调试的驱动程序任务。与调试器合作的多任务内核将在同一机器的不同线程上运行每个元素，从而允许调试器和驱动程序任务被调试以继续运行，而不停止图形用户界面或操作系统的操作与图形用户界面相关联。

4. 发明申请

US20130013905A1 BIOS FLASH ATTACK PROTECTION AND NOTIFICATION 有权
标题翻译： BIOS闪存攻击保护和通知
公开(公告)号：US20130013905A1
公开(公告)日：2013-01-10
申请号：US13178338
申请日：2011-07-07
申请人： James P. Held , Scott H. Robinson , Vincent J. Zimmer
发明人： James P. Held , Scott H. Robinson , Vincent J. Zimmer
IPC分类号： G06F9/00
CPC分类号： G06F21/575 , G06F9/4401 , G06F21/64
摘要： A system and method for BIOS flash attack protection and notification. A processor initialization module, including initialization firmware verification module may be configured to execute first in response to a power on and/or reset and to verify initialization firmware stored in non-volatile memory in a processor package. The initialization firmware is configured to verify the BIOS. If the verification of the initialization firmware and/or the BIOS fails, the system is configured to select at least one of a plurality of responses including, but not limited to, preventing the BIOS from executing, initiating recovery, reporting the verification failure, halting, shutting down and/or allowing the BIOS to execute and an operating system (OS) to boot in a limited functionality mode.
摘要翻译：用于BIOS闪存防护和通知的系统和方法。包括初始化固件验证模块的处理器初始化模块可以被配置为响应于电源接通和/或复位而首先执行并且验证处理器封装中存储在非易失性存储器中的初始化固件。初始化固件配置为验证BIOS。如果初始化固件和/或BIOS的验证失败，则系统被配置为选择多个响应中的至少一个，包括但不限于防止BIOS执行，启动恢复，报告验证失败，停止，关闭和/或允许BIOS执行，以及操作系统（OS）以有限的功能模式进行引导。

5. 发明申请

US20110072234A1 Providing Hardware Support For Shared Virtual Memory Between Local And Remote Physical Memory 有权
标题翻译：为本地和远程物理内存之间的共享虚拟内存提供硬件支持
公开(公告)号：US20110072234A1
公开(公告)日：2011-03-24
申请号：US12562477
申请日：2009-09-18
申请人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
发明人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1036 , G06F12/1027 , G06F12/121 , G06F2212/254
摘要： In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程记忆。以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。描述和要求保护其他实施例。

6. 发明授权

US09747118B2 Guest-specific microcode 有权
公开(公告)号：US09747118B2
公开(公告)日：2017-08-29
申请号：US12349307
申请日：2009-01-06
申请人： Richard L. Maliszewski , James P. Held , Daniel Baumberger
发明人： Richard L. Maliszewski , James P. Held , Daniel Baumberger
IPC分类号： G06F9/30 , G06F9/455 , G06F9/22
CPC分类号： G06F9/45533 , G06F9/22 , G06F9/30174 , G06F9/30189
摘要： Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an apparatus includes virtualization logic, first storage, second storage, decode logic, and multiplexing logic. The virtualization logic is to provide a mode in which to operate a virtual machine. The first storage is to store a first plurality of micro-instructions to control the apparatus. The second storage is to store a second plurality of micro-instructions to control the apparatus. The decode logic is to decode a macro-instruction into one of a first plurality and a second plurality of micro-instructions. The multiplexing logic is to cause the macro-instruction to be decoded into the second plurality of micro-instructions instead of the first plurality of micro-instructions only when issued from the virtual machine.

7. 发明授权

US08521969B2 Apparatus and method for directing micro architectural memory region accesses 有权
标题翻译：用于指导微架构存储器区域访问的装置和方法
公开(公告)号：US08521969B2
公开(公告)日：2013-08-27
申请号：US11546710
申请日：2006-10-11
申请人： Martin G. Dixon , Scott D. Rodgers , James P. Held , Bill Alexander , Larry O. Smith , Scott H. Robinson , Sham M. Datta
发明人： Martin G. Dixon , Scott D. Rodgers , James P. Held , Bill Alexander , Larry O. Smith , Scott H. Robinson , Sham M. Datta
IPC分类号： G06F12/00
CPC分类号： G06F21/79 , G06F12/1441 , G06F2221/2141
摘要： In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.
摘要翻译：在一个实施例中，存储在系统存储器内的信息的存储器访问请求通过集成电路。系统存储器可以包括用于存储指令和/或数据的微架构存储器区域，其中微架构存储器区域将被微架构代理程序唯一地访问。集成电路可以包括存储器访问控制器以引导存储器访问请求如果存储器访问指导者确定存储器访问请求包括至少一个微架构存储器区域内的位置，并且微架构代理程序在微架构存储器区域访问模式下操作，则向微架构存储器区域发送。

8. 发明授权

US5809317A Creating and maintaining hypertext links among heterogeneous documents by the establishment of anchors and connections among anchors 失效
标题翻译：通过在锚点之间建立锚点和连接来创建和维护异构文档之间的超文本链接
公开(公告)号：US5809317A
公开(公告)日：1998-09-15
申请号：US869499
申请日：1997-06-05
申请人： Dan D. Kogan , Paul C. Drews , James P. Held , James A. Larson
发明人： Dan D. Kogan , Paul C. Drews , James P. Held , James A. Larson
IPC分类号： G06F17/30
CPC分类号： G06F17/30014
摘要： A method and apparatus for relating (called hyperlinking) a region of one document to one or more regions of other documents. This is provided by using a mechanism for linking and embedding objects to establish the endpoints of the hyperlinks (called anchors) together with the creation of intermediate tables which maintain information about relations between regions of documents and attributes of the relationship. When a user selects a region in a document which participates in a relationship, a database program is invoked which displays information about related regions in other documents which may be accessed through the intermediate tables. An auxiliary table maintains information about attributes which may be custom designed by the user, such as author, date of creation, etc. The intermediate tables allow relationships among multiple regions of documents created by different applications. Relationships are bidirectional in that the user can traverse from any region in a document to any other region in the same relationship.
摘要翻译：将一个文档的区域（称为超链接）与其他文档的一个或多个区域相关联的方法和装置。这通过使用用于链接和嵌入对象以建立超链接的端点（称为锚点）的机制以及维护关于文档区域与关系的属性之间的关系的中间表的创建来提供。当用户选择参与关系的文档中的区域时，调用数据库程序，其显示可以通过中间表访问的其他文档中的相关区域的信息。辅助表维护关于可由用户定制设计的属性的信息，例如作者，创建日期等。中间表允许由不同应用创建的文档的多个区域之间的关系。关系是双向的，因为用户可以从文档中的任何区域遍历到相同关系中的任何其他区域。

9. 发明申请

US20140208042A1 PROVIDING HARDWARE SUPPORT FOR SHARED VIRTUAL MEMORY BETWEEN LOCAL AND REMOTE PHYSICAL MEMORY 审中-公开
标题翻译：为当地和远程物理内存之间的共享虚拟内存提供硬件支持
公开(公告)号：US20140208042A1
公开(公告)日：2014-07-24
申请号：US14221741
申请日：2014-03-21
申请人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
发明人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/1036 , G06F12/1027 , G06F12/121 , G06F2212/254
摘要： In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程记忆。以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。描述和要求保护其他实施例。

10. 发明申请

US20100174889A1 GUEST-SPECIFIC MICROCODE 有权
标题翻译：专用微型计算机
公开(公告)号：US20100174889A1
公开(公告)日：2010-07-08
申请号：US12349307
申请日：2009-01-06
申请人： Richard L. Maliszewski , James P. Held , Daniel Baumberger
发明人： Richard L. Maliszewski , James P. Held , Daniel Baumberger
IPC分类号： G06F9/455 , G06F9/30
CPC分类号： G06F9/45533 , G06F9/22 , G06F9/30174 , G06F9/30189
摘要： Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an apparatus includes virtualization logic, first storage, second storage, decode logic, and multiplexing logic. The virtualization logic is to provide a mode in which to operate a virtual machine. The first storage is to store a first plurality of micro-instructions to control the apparatus. The second storage is to store a second plurality of micro-instructions to control the apparatus. The decode logic is to decode a macro-instruction into one of a first plurality and a second plurality of micro-instructions. The multiplexing logic is to cause the macro-instruction to be decoded into the second plurality of micro-instructions instead of the first plurality of micro-instructions only when issued from the virtual machine.
摘要翻译：公开了用于修改安装在VM内运行的客户端的行为的装置，方法和系统的实施例。在一个实施例中，设备包括虚拟化逻辑，第一存储，第二存储，解码逻辑和多路复用逻辑。虚拟化逻辑是提供一种操作虚拟机的模式。第一存储器是存储第一多个微指令以控制该装置。第二存储器是存储第二多个微指令以控制该装置。解码逻辑是将宏指令解码为第一多个和第二多个微指令之一。复用逻辑是仅在从虚拟机发出时，使宏指令被解码成第二多个微指令而不是第一多个微指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式