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1. 发明申请

US20110161676A1 ENTERING A SECURED COMPUTING ENVIRONMENT USING MULTIPLE AUTHENTICATED CODE MODULES 有权
标题翻译：使用多个授权代码模块进入安全的计算环境
公开(公告)号：US20110161676A1
公开(公告)日：2011-06-30
申请号：US12650579
申请日：2009-12-31
申请人： Sham M. Datta , Ernie F. Brickell , Mohan J. Kumar
发明人： Sham M. Datta , Ernie F. Brickell , Mohan J. Kumar
IPC分类号： G06F21/00
CPC分类号： G06F21/00 , G06F21/57 , G06F21/572 , G06F21/71 , G06F2221/2149 , G06F2221/2153
摘要： Systems, apparatuses, and methods, and for entering a secured system environment using multiple authenticated code modules are disclosed. In one embodiment, a processor includes a decoder and control logic. The decoder is to decode a secured enter instruction. The control logic is to find an entry corresponding to the processor in a match table in a master authenticated code module and to read a master header and an individual authenticated code module from the master authenticated code module in response to decoding the secured enter instruction.
摘要翻译：公开了系统，装置和方法以及使用多个认证代码模块输入安全系统环境。在一个实施例中，处理器包括解码器和控制逻辑。解码器是对安全的输入指令进行解码。控制逻辑是在主认证代码模块的匹配表中找到与处理器相对应的条目，并且响应于对安全的进入指令进行解码，从主认证代码模块读取主标题和单独的认证代码模块。

2. 发明申请

US20130103938A1 Reconfiguring A Secure System 有权
标题翻译：重新配置安全系统
公开(公告)号：US20130103938A1
公开(公告)日：2013-04-25
申请号：US13664930
申请日：2012-10-31
申请人： Sham M. Datta , Mohan J. Kumar , Ernie Brickell , Ioannis T. Schoinas , James A. Sutton
发明人： Sham M. Datta , Mohan J. Kumar , Ernie Brickell , Ioannis T. Schoinas , James A. Sutton
IPC分类号： G06F21/00
CPC分类号： G06F21/57
摘要： Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.
摘要翻译：公开了用于重新配置安全系统的装置，方法和系统。在一个实施例中，装置包括配置存储位置，锁定和锁定超驰逻辑。配置存储位置是存储信息以配置设备。该锁是为了防止写入配置存储位置。锁定覆盖逻辑是允许从子操作模式代码执行的指令覆盖锁定。

3. 发明授权

US08316414B2 Reconfiguring a secure system 有权
标题翻译：重新配置安全系统
公开(公告)号：US08316414B2
公开(公告)日：2012-11-20
申请号：US11618649
申请日：2006-12-29
申请人： Sham M. Datta , Mohan J. Kumar , James A. Sutton , Ernie Brickell , Ioannis T. Schoinas
发明人： Sham M. Datta , Mohan J. Kumar , James A. Sutton , Ernie Brickell , Ioannis T. Schoinas
IPC分类号： G06F21/00
CPC分类号： G06F21/57
摘要： Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.
摘要翻译：公开了用于重新配置安全系统的装置，方法和系统。在一个实施例中，装置包括配置存储位置，锁定和锁定超驰逻辑。配置存储位置是存储信息以配置设备。该锁是为了防止写入配置存储位置。锁定覆盖逻辑是允许从子操作模式代码执行的指令覆盖锁定。

4. 发明授权

US07725637B2 Methods and apparatus for generating system management interrupts 有权
标题翻译：产生系统管理中断的方法和装置
公开(公告)号：US07725637B2
公开(公告)日：2010-05-25
申请号：US11967299
申请日：2007-12-31
申请人： Mohan Kumar , Sarathy Jayakumar , Sham M Datta
发明人： Mohan Kumar , Sarathy Jayakumar , Sham M Datta
IPC分类号： G06F13/24
CPC分类号： G06F9/4812
摘要： A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.
摘要翻译：一种方法包括确定多个存储器地址，每个存储器地址彼此不同。该方法还包括产生多个系统管理中断处理器中断，每个系统管理中断处理器中断在系统中的多个处理器中具有对应的处理器，并且每个系统管理中断处理器中断包括多个存储器地址之一。该方法还包括将每个系统管理中断处理器中断引导到相应的处理器。还公开了一种相关的机器可读介质。

5. 发明申请

US20090172385A1 ENABLING SYSTEM MANAGEMENT MODE IN A SECURE SYSTEM 有权
标题翻译：在安全系统中启用系统管理模式
公开(公告)号：US20090172385A1
公开(公告)日：2009-07-02
申请号：US11967779
申请日：2007-12-31
申请人： Sham M. Datta , Mohan J. Kumar , Maheeh Natu
发明人： Sham M. Datta , Mohan J. Kumar , Maheeh Natu
IPC分类号： G06F9/00
CPC分类号： G06F9/30087 , G06F9/45533
摘要： Apparatuses, methods, and systems for enabling system management mode in a secure system are disclosed. In one embodiment, a processor includes sub-operating-system mode logic, virtual machine logic, and control logic. The sub-operating-system mode logic is to support a sub-operating-system mode. The virtual machine logic is to support virtualization. The control logic is to prevent virtualization from being enabled when the sub-operating-system mode is disabled.
摘要翻译：公开了一种用于在安全系统中启用系统管理模式的装置，方法和系统。在一个实施例中，处理器包括子操作系统模式逻辑，虚拟机逻辑和控制逻辑。子操作系统模式逻辑是支持子操作系统模式。虚拟机逻辑是支持虚拟化。控制逻辑是防止在禁用子操作系统模式时启用虚拟化。

6. 发明授权

US07254676B2 Processor cache memory as RAM for execution of boot code 有权
标题翻译：处理器缓存内存作为执行启动代码的RAM
公开(公告)号：US07254676B2
公开(公告)日：2007-08-07
申请号：US10295406
申请日：2002-11-15
申请人： Sham M. Datta , Vincent J. Zimmer , Kushagra V. Vaid , William A. Stevens , Amy Lynn Santoni
发明人： Sham M. Datta , Vincent J. Zimmer , Kushagra V. Vaid , William A. Stevens , Amy Lynn Santoni
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F9/4403 , G06F12/0862 , G06F2212/2515
摘要： In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.
摘要翻译：在一个实施例中，计算机引导方法允许为具有多个交叉处理器交互的高速缓存选择预定数据块对齐。作为RAM系统的缓存的高速缓存RAM列被加载有标签以防止意外的高速缓存行驱逐，并且执行引导代码，其中预先加载的高速缓存RAM作为存储器存储器显示在执行的引导代码流中。

7. 发明授权

US5671422A Method and apparatus for switching between the modes of a processor 失效
标题翻译：用于在处理器的模式之间切换的方法和装置
公开(公告)号：US5671422A
公开(公告)日：1997-09-23
申请号：US411450
申请日：1995-03-28
申请人： Sham M. Datta
发明人： Sham M. Datta
IPC分类号： G06F9/32 , G06F9/48 , G06F9/00
CPC分类号： G06F9/4812
摘要： A method for switching between a first mode and a second mode of a processor is provided. According to one embodiment of the invention, a computer system includes the processor coupled to a storage device storing a number of instructions. In response to a first interrupt, a first information is stored in the storage device for switching to processing in the first mode starting at a first of the number of instructions. In response to a second interrupt occurring subsequent to the storing of the first information, said processor switches from processing in the first mode to processing in the second mode. Also in response to the second interrupt, a second information is storm in the storage device for returning to processing in the first mode starting at a second of the number of instructions. In response to said processor switching from said first mode to said second mode, said processor switches from processing in the second mode to processing in the first mode starting at the first instruction using the first information if processing starting at the first instruction is required.
摘要翻译：提供了一种用于在处理器的第一模式和第二模式之间切换的方法。根据本发明的一个实施例，计算机系统包括耦合到存储多个指令的存储设备的处理器。响应于第一中断，第一信息被存储在存储设备中，用于在第一模式中的第一个指令开始处切换到处理。响应于在存储第一信息之后发生的第二中断，所述处理器从第一模式的处理切换到第二模式的处理。此外，响应于第二中断，第二信息在存储设备中暴风雨，以在指令数量的第二位置从第一模式返回到处理。响应于所述处理器从所述第一模式切换到所述第二模式，如果需要从第一指令开始的处理，则所述处理器从第二模式的处理切换到从第一指令开始的处理，使用第一信息。

8. 发明授权

US09202015B2 Entering a secured computing environment using multiple authenticated code modules 有权
标题翻译：使用多个经过身份验证的代码模块进入安全的计算环境
公开(公告)号：US09202015B2
公开(公告)日：2015-12-01
申请号：US12650579
申请日：2009-12-31
申请人： Sham M. Datta , Ernie F. Brickell , Mohan J. Kumar
发明人： Sham M. Datta , Ernie F. Brickell , Mohan J. Kumar
IPC分类号： G06F21/00 , G06F21/57 , G06F21/71
CPC分类号： G06F21/00 , G06F21/57 , G06F21/572 , G06F21/71 , G06F2221/2149 , G06F2221/2153
摘要： Systems, apparatuses, and methods, and for entering a secured system environment using multiple authenticated code modules are disclosed. In one embodiment, a processor includes a decoder and control logic. The decoder is to decode a secured enter instruction. The control logic is to find an entry corresponding to the processor in a match table in a master authenticated code module and to read a master header and an individual authenticated code module from the master authenticated code module in response to decoding the secured enter instruction.
摘要翻译：公开了系统，装置和方法以及使用多个认证代码模块输入安全系统环境。在一个实施例中，处理器包括解码器和控制逻辑。解码器是对安全的输入指令进行解码。控制逻辑是在主认证代码模块的匹配表中找到与处理器相对应的条目，并且响应于对安全的进入指令进行解码，从主认证代码模块读取主标题和单独的认证代码模块。

9. 发明授权

US08473945B2 Enabling system management mode in a secure system 有权
标题翻译：在安全系统中启用系统管理模式
公开(公告)号：US08473945B2
公开(公告)日：2013-06-25
申请号：US11967779
申请日：2007-12-31
申请人： Sham M. Datta , Mohan J. Kumar , Maheeh Natu
发明人： Sham M. Datta , Mohan J. Kumar , Maheeh Natu
IPC分类号： G06F9/455
CPC分类号： G06F9/30087 , G06F9/45533
摘要： Apparatuses, methods, and systems for enabling system management mode in a secure system are disclosed. In one embodiment, a processor includes sub-operating-system mode logic, virtual machine logic, and control logic. The sub-operating-system mode logic is to support a sub-operating-system mode. The virtual machine logic is to support virtualization. The control logic is to prevent virtualization from being enabled when the sub-operating-system mode is disabled.
摘要翻译：公开了一种用于在安全系统中启用系统管理模式的装置，方法和系统。在一个实施例中，处理器包括子操作系统模式逻辑，虚拟机逻辑和控制逻辑。子操作系统模式逻辑是支持子操作系统模式。虚拟机逻辑是支持虚拟化。控制逻辑是防止在禁用子操作系统模式时启用虚拟化。

10. 发明授权

US08423682B2 Address space emulation 有权
标题翻译：地址空间仿真
公开(公告)号：US08423682B2
公开(公告)日：2013-04-16
申请号：US11323465
申请日：2005-12-30
申请人： Sham M. Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
发明人： Sham M. Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
IPC分类号： G06F3/00 , G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F9/342 , G06F9/30174 , G06F12/0292 , G06F12/063 , G06F2212/206
摘要： Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.
摘要翻译：装置和系统以及方法和物品可以操作以检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问操作。配置存储器地址和相关联的配置数据可以被组合成具有大于第一存储器地址位大小（例如，32位）的第二存储器地址位大小（例如，64位）的分组。该分组可以用于为尝试与外围组件互连（PCI）接口的外围设备以及已经集成到与处理器相同的封装中的类似的平台设备进行通信的传统操作系统建立兼容性。

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