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1. 发明申请

US20060046370A1 Method of manufacturing a transistor with void-free gate electrode 审中-公开
标题翻译：制造无空隙栅电极晶体管的方法
公开(公告)号：US20060046370A1
公开(公告)日：2006-03-02
申请号：US11210820
申请日：2005-08-25
申请人： Yong-chul Oh , Wook-je Kim , Dong-gun Park , Woun-suck Yang
发明人： Yong-chul Oh , Wook-je Kim , Dong-gun Park , Woun-suck Yang
IPC分类号： H01L21/8238 , H01L21/425 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28035 , H01L21/28061 , H01L21/3212 , H01L21/823842
摘要： A method of manufacturing a MOS transistor with a void-free gate electrode is provided. A gate oxide film may be formed on a semiconductor, and a poly silicon film for a gate electrode may be deposited on the gate oxide film. P-type impurities may be implanted into the poly silicon film, and a thickness of the poly silicon film may be removed by chemical mechanical polishing.
摘要翻译：提供一种制造具有无空隙栅电极的MOS晶体管的方法。可以在半导体上形成栅极氧化膜，并且可以在栅极氧化膜上沉积用于栅电极的多晶硅膜。可以将P型杂质注入到多晶硅膜中，并且可以通过化学机械抛光去除多晶硅膜的厚度。

2. 发明授权

US07977725B2 Integrated circuit semiconductor device including stacked level transistors 有权
标题翻译：集成电路半导体器件，包括层叠晶体管
公开(公告)号：US07977725B2
公开(公告)日：2011-07-12
申请号：US12171091
申请日：2008-07-10
申请人： Jae-man Yoon , Yong-chul Oh , Hui-jung Kim , Hyun-woo Chung , Kang-uk Kim , Dong-gun Park , Woun-suck Yang
发明人： Jae-man Yoon , Yong-chul Oh , Hui-jung Kim , Hyun-woo Chung , Kang-uk Kim , Dong-gun Park , Woun-suck Yang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10894 , H01L21/8221 , H01L27/0688 , H01L27/10817 , H01L27/10876 , H01L27/10897 , H01L29/66666
摘要： An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer.
摘要翻译：集成电路半导体器件包括形成在下基板处并配置有垂直晶体管和平面晶体管中的至少一个的第一晶体管。在第一晶体管上形成接合绝缘层，并且在接合绝缘层上接合上基板。在上基板上形成配置有垂直晶体管和平面晶体管中的至少一个的第二晶体管。第一晶体管和第二晶体管通过互连层连接。

3. 发明申请

US20090108318A1 Integrated Circuit Semiconductor Device Including Stacked Level Transistors and Fabrication Method Thereof 有权
标题翻译：包括层叠晶体管的集成电路半导体器件及其制造方法
公开(公告)号：US20090108318A1
公开(公告)日：2009-04-30
申请号：US12171091
申请日：2008-07-10
申请人： Jae-man Yoon , Yong-chul Oh , Hui-jung Kim , Hyun-woo Chung , Kang-uk Kim , Dong-gun Park , Woun-suck Yang
发明人： Jae-man Yoon , Yong-chul Oh , Hui-jung Kim , Hyun-woo Chung , Kang-uk Kim , Dong-gun Park , Woun-suck Yang
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L21/8221 , H01L27/0688 , H01L27/10817 , H01L27/10876 , H01L27/10897 , H01L29/66666
摘要： An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer.
摘要翻译：集成电路半导体器件包括形成在下基板处并配置有垂直晶体管和平面晶体管中的至少一个的第一晶体管。在第一晶体管上形成接合绝缘层，并且在接合绝缘层上接合上基板。在上基板上形成配置有垂直晶体管和平面晶体管中的至少一个的第二晶体管。第一晶体管和第二晶体管通过互连层连接。

4. 发明授权

US08283714B2 Semiconductor memory device having vertical channel transistor and method for fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及其制造方法
公开(公告)号：US08283714B2
公开(公告)日：2012-10-09
申请号：US13085898
申请日：2011-04-13
申请人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
发明人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
IPC分类号： H01L29/94
CPC分类号： H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
摘要翻译：两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件。像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

5. 发明授权

US07859064B1 Semiconductor devices including channel and junction regions of different semiconductor materials 有权
标题翻译：半导体器件包括不同半导体材料的沟道和结区
公开(公告)号：US07859064B1
公开(公告)日：2010-12-28
申请号：US11849577
申请日：2007-09-04
申请人： Chang-woo Oh , Dong-gun Park , Dong-won Kim , Sung-dae Suk
发明人： Chang-woo Oh , Dong-gun Park , Dong-won Kim , Sung-dae Suk
IPC分类号： H01L29/41
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.
摘要翻译：半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

6. 发明申请

US20100285645A1 METHODS OF MANUFACTURING VERTICAL CHANNEL SEMICONDUCTOR DEVICES 有权
标题翻译：制造垂直通道半导体器件的方法
公开(公告)号：US20100285645A1
公开(公告)日：2010-11-11
申请号：US12838826
申请日：2010-07-19
申请人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Choong-Ho Lee , Seong-Goo Kim , Won-sok Lee , Seung-bae Park
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11568 , H01L28/91 , H01L29/66833 , H01L29/7926
摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.
摘要翻译：垂直沟道半导体器件包括具有上表面的柱的半导体衬底。绝缘栅电极围绕柱的周边。绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。第一源极/漏极区域在与衬底相邻的衬底中。第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

7. 发明授权

US07602010B2 Multi-bit multi-level non-volatile memory device and methods of operating and fabricating the same 有权
标题翻译：多位多级非易失性存储器件及其操作和制造方法
公开(公告)号：US07602010B2
公开(公告)日：2009-10-13
申请号：US11407133
申请日：2006-04-19
申请人： Byung-yong Choi , Tae-yong Kim , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho , Dong-gun Park , Choong-ho Lee
发明人： Byung-yong Choi , Tae-yong Kim , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho , Dong-gun Park , Choong-ho Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/4232 , H01L29/66825 , H01L29/66833 , H01L29/7851
摘要： In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate electrodes, formed at least at surface regions of the sidewalls of the fins between the source and the drain regions.
摘要翻译：在允许多位和/或多电平操作的非易失性存储器件及其操作和制造方法中，非易失性存储器件在一个实施例中包括：半导体衬底，掺杂有第一导电型，其具有由形成在基板中的至少两个分开的沟槽限定的一个或多个散热片，散热片沿第一方向沿着基板延伸; 成对的栅电极在散热片的侧壁处形成为间隔物，其中栅电极与包括散热片的半导体基板绝缘，并平行于翅片延伸; 栅电极和鳍之间的存储节点，并与栅电极和半导体衬底绝缘; 源极区域和漏极区域，其掺杂有第二导电类型的杂质，并且分别形成在鳍片的至少在表面部分并且延伸穿过翅片的第一方向; 以及对应于各个栅电极的沟道区，至少在源极和漏极区之间的翅片的侧壁的表面区域处形成。

8. 发明授权

US07511358B2 Nonvolatile memory device having multi-bit storage and method of manufacturing the same 有权
标题翻译：具有多位存储器的非易失性存储器件及其制造方法
公开(公告)号：US07511358B2
公开(公告)日：2009-03-31
申请号：US11517595
申请日：2006-09-07
申请人： Byung-yong Choi , Choong-ho Lee , Dong-gun Park
发明人： Byung-yong Choi , Choong-ho Lee , Dong-gun Park
IPC分类号： H01L29/06
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/7851 , H01L29/7887
摘要： Provided are a nonvolatile memory device having multi bit storage and a method of manufacturing the same. The method includes forming a tunneling dielectric layer, a charge storage layer and a charge blocking layer on a fin-active region, forming sacrificial patterns having a groove to open a crossing region of the active region on the charge blocking layer, selectively removing portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer exposed by the opening groove using the sacrificial layer patterns as an etch mask to expose a top surface and side surfaces of the active region, forming a gate dielectric layer on exposed portion of the active region to cover exposed side surfaces of the of charge storage layer, forming a first gate on the gate dielectric layer to fill the groove, removing the sacrificial layer patterns, forming second gates on side surfaces of the first gate, forming isolated local charge storage patterns, charge blocking patterns and tunneling dielectric patterns by selectively removing exposed portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer, and forming a source/drain region on the active region.
摘要翻译：提供一种具有多位存储器的非易失性存储器件及其制造方法。该方法包括在鳍片活性区域上形成隧穿介质层，电荷存储层和电荷阻挡层，形成具有凹槽的牺牲图案，以打开电荷阻挡层上的有源区的交叉区域，电荷阻挡层，电荷存储层和隧道电介质层，其使用牺牲层图案作为蚀刻掩模暴露于开口槽，以暴露有源区的顶表面和侧表面，在暴露部分上形成栅极电介质层所述有源区域覆盖电荷存储层的暴露的侧表面，在栅极电介质层上形成第一栅极以填充沟槽，去除牺牲层图案，在第一栅极的侧表面上形成第二栅极，形成隔离的局部电荷存储图案，电荷阻挡图案和隧道电介质图案，通过选择性地去除电荷阻挡层的暴露部分 r，电荷存储层和隧道电介质层，并且在有源区上形成源/漏区。

9. 发明申请

US20080211013A1 SEMICONDUCTOR MEMORY DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有垂直通道晶体管的半导体存储器件及其制造方法
公开(公告)号：US20080211013A1
公开(公告)日：2008-09-04
申请号：US12118268
申请日：2008-05-09
申请人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
发明人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/66666 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/7827
摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.
摘要翻译：在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。形成围绕每个支柱部分的栅电极。位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。第一掺杂区域形成在柱的每个柱部分的上表面中。第二掺杂区形成在柱的主体部分上并与电位线连接。存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

10. 发明申请

US20080111180A1 SPLIT GATE FLASH MEMORY DEVICE HAVING SELF-ALIGNED CONTROL GATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有自对准控制门的分离闸门闪存存储器件及其制造方法
公开(公告)号：US20080111180A1
公开(公告)日：2008-05-15
申请号：US12014262
申请日：2008-01-15
申请人： Byung-yong Choi , Chang-woo Oh , Dong-gun Park , Dong-won Kim , Yong-kyu Lee
发明人： Byung-yong Choi , Chang-woo Oh , Dong-gun Park , Dong-won Kim , Yong-kyu Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L29/42324 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.
摘要翻译：在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点控制栅极和半导体衬底之间的区域。每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。一对间隔物控制栅极围绕源极区域彼此大致对称。

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