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1. 发明申请

US20060046370A1 Method of manufacturing a transistor with void-free gate electrode 审中-公开
标题翻译：制造无空隙栅电极晶体管的方法
公开(公告)号：US20060046370A1
公开(公告)日：2006-03-02
申请号：US11210820
申请日：2005-08-25
申请人： Yong-chul Oh , Wook-je Kim , Dong-gun Park , Woun-suck Yang
发明人： Yong-chul Oh , Wook-je Kim , Dong-gun Park , Woun-suck Yang
IPC分类号： H01L21/8238 , H01L21/425 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28035 , H01L21/28061 , H01L21/3212 , H01L21/823842
摘要： A method of manufacturing a MOS transistor with a void-free gate electrode is provided. A gate oxide film may be formed on a semiconductor, and a poly silicon film for a gate electrode may be deposited on the gate oxide film. P-type impurities may be implanted into the poly silicon film, and a thickness of the poly silicon film may be removed by chemical mechanical polishing.
摘要翻译：提供一种制造具有无空隙栅电极的MOS晶体管的方法。可以在半导体上形成栅极氧化膜，并且可以在栅极氧化膜上沉积用于栅电极的多晶硅膜。可以将P型杂质注入到多晶硅膜中，并且可以通过化学机械抛光去除多晶硅膜的厚度。

2. 发明授权

US07977725B2 Integrated circuit semiconductor device including stacked level transistors 有权
标题翻译：集成电路半导体器件，包括层叠晶体管
公开(公告)号：US07977725B2
公开(公告)日：2011-07-12
申请号：US12171091
申请日：2008-07-10
申请人： Jae-man Yoon , Yong-chul Oh , Hui-jung Kim , Hyun-woo Chung , Kang-uk Kim , Dong-gun Park , Woun-suck Yang
发明人： Jae-man Yoon , Yong-chul Oh , Hui-jung Kim , Hyun-woo Chung , Kang-uk Kim , Dong-gun Park , Woun-suck Yang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10894 , H01L21/8221 , H01L27/0688 , H01L27/10817 , H01L27/10876 , H01L27/10897 , H01L29/66666
摘要： An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer.
摘要翻译：集成电路半导体器件包括形成在下基板处并配置有垂直晶体管和平面晶体管中的至少一个的第一晶体管。在第一晶体管上形成接合绝缘层，并且在接合绝缘层上接合上基板。在上基板上形成配置有垂直晶体管和平面晶体管中的至少一个的第二晶体管。第一晶体管和第二晶体管通过互连层连接。

3. 发明申请

US20090108318A1 Integrated Circuit Semiconductor Device Including Stacked Level Transistors and Fabrication Method Thereof 有权
标题翻译：包括层叠晶体管的集成电路半导体器件及其制造方法
公开(公告)号：US20090108318A1
公开(公告)日：2009-04-30
申请号：US12171091
申请日：2008-07-10
申请人： Jae-man Yoon , Yong-chul Oh , Hui-jung Kim , Hyun-woo Chung , Kang-uk Kim , Dong-gun Park , Woun-suck Yang
发明人： Jae-man Yoon , Yong-chul Oh , Hui-jung Kim , Hyun-woo Chung , Kang-uk Kim , Dong-gun Park , Woun-suck Yang
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L21/8221 , H01L27/0688 , H01L27/10817 , H01L27/10876 , H01L27/10897 , H01L29/66666
摘要： An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer.
摘要翻译：集成电路半导体器件包括形成在下基板处并配置有垂直晶体管和平面晶体管中的至少一个的第一晶体管。在第一晶体管上形成接合绝缘层，并且在接合绝缘层上接合上基板。在上基板上形成配置有垂直晶体管和平面晶体管中的至少一个的第二晶体管。第一晶体管和第二晶体管通过互连层连接。

4. 发明授权

US08154065B2 Semiconductor memory devices including a vertical channel transistor having a buried bit line 有权
标题翻译：半导体存储器件包括具有埋入位线的垂直沟道晶体管
公开(公告)号：US08154065B2
公开(公告)日：2012-04-10
申请号：US12418879
申请日：2009-04-06
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译：半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。相邻的围绕电极围绕其中的一个柱。第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极地区。

5. 发明授权

US08044451B2 Method of manufacturing semiconductor device having notched gate MOSFET 有权
标题翻译：具有开槽栅极MOSFET的半导体器件的制造方法
公开(公告)号：US08044451B2
公开(公告)日：2011-10-25
申请号：US12498615
申请日：2009-07-07
申请人： Byung-yong Choi , Choong-ho Lee , Dong-won Kim , Dong-gun Park
发明人： Byung-yong Choi , Choong-ho Lee , Dong-won Kim , Dong-gun Park
IPC分类号： H01L29/788
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66537 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.
摘要翻译：提供一种制造半导体器件的方法，通过该方法，形成在半导体衬底的单元阵列区域上的单元晶体管采用其中使用间隔物形状的电极形成栅极并且多位操作是可能使用局部位，并且可以在作为半导体衬底的剩余区域的外围电路区域上形成具有根据晶体管的功能而被优化以满足不同要求的结构的晶体管。在该方法中，在单元阵列区域上形成单元晶体管。单元晶体管包括陷波门结构，在陷波栅结构下形成在半导体衬底上的第一沟道区，形成在第一沟道区的两侧的源区和漏区，形成在第一沟道区之间的第一栅极绝缘膜沟道区域和陷波门结构，以及局部地形成在与第一沟道区和陷波栅结构之间的源极和漏极区相邻的区域上的存储层。在形成单元晶体管的同时，在外围电路区域上形成有包含至少一个具有与单元晶体管不同的结构的晶体管的多个外围电路晶体管。

6. 发明申请

US20100244124A1 SEMICONDUCTOR DEVICES HAVING A VERTICAL CHANNEL TRANSISTOR 有权
标题翻译：具有垂直通道晶体管的半导体器件
公开(公告)号：US20100244124A1
公开(公告)日：2010-09-30
申请号：US12814121
申请日：2010-06-11
申请人： Hyeoung-won Seo , Jae-man Yoon , Dong-gun Park , Seong-goo Kim
发明人： Hyeoung-won Seo , Jae-man Yoon , Dong-gun Park , Seong-goo Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/105 , H01L29/42356 , H01L29/4236 , H01L29/42376 , H01L29/66666 , H01L29/78642
摘要： Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.
摘要翻译：根据本发明构思的实施例可以提供半导体器件，其包括衬底和布置在衬底上的矩阵中的多个有源柱。每个支柱包括通道部分，其包括设置在通道部分的表面中的通道掺杂剂区域。栅电极围绕通道部分的外表面。多个有源支柱可以沿着第一方向排成行，并且在与第一方向交叉的第二方向上列排列。

7. 发明授权

US07675105B2 Non-volatile memory device for 2-bit operation and method of fabricating the same 失效
标题翻译：用于2位操作的非易失性存储器件及其制造方法
公开(公告)号：US07675105B2
公开(公告)日：2010-03-09
申请号：US11376518
申请日：2006-03-15
申请人： Byung-yong Choi , Dong-gun Park , Yun-gi Kim , Choong-ho Lee , Young-mi Lee , Hye-jin Cho
发明人： Byung-yong Choi , Dong-gun Park , Yun-gi Kim , Choong-ho Lee , Young-mi Lee , Hye-jin Cho
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.
摘要翻译：提供了一种用于2位操作的非易失性存储器件及其制造方法。非易失性存储器件包括在半导体衬底上沿着字线方向延伸的有源区和栅极，并且重复地交叉; 电荷存储层，设置在所述栅极的下方，并限制在所述栅极和所述有源区域交叉的部分; 形成在电荷存储层上的电荷阻挡层; 形成在电荷存储层下面的隧道介电层; 在由栅极暴露的有源区中形成的第一和第二源/漏区; 以及与字线方向交叉的第一和第二位线。有源区可以形成为第一之字形图案和/或栅极可以以与第一曲折图案对称的第二曲折图案形成。

8. 发明授权

US07586149B2 Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same 有权
标题翻译：电路装置包括连接到埋地位线的垂直晶体管及其制造方法
公开(公告)号：US07586149B2
公开(公告)日：2009-09-08
申请号：US11541756
申请日：2006-10-02
申请人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
IPC分类号： H01L23/528 , H01L27/108
CPC分类号： H01L29/66666 , H01L21/823885 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.
摘要翻译：一种包括连接到掩埋位线的垂直晶体管的电路器件和制造该电路器件的方法。该电路装置包括半导体衬底，该半导体衬底包括外围电路区域和在外围电路区域的两侧的左侧和右侧电池区域，布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并从所述外围电路区域与所述左侧单元区域和右侧单元区域交替地排列成行方向，所述通道柱从所述底部有源区域沿垂直方向突出并且被配置为在所述行方向上彼此对准并且彼此间隔开，栅电极设置有栅介电层并且被附接到环绕通道柱的侧表面，以及沿底部有源区延伸的掩埋位线，底部有源区包括底部源极/漏极区。

9. 发明申请

US20090189217A1 Semiconductor Memory Devices Including a Vertical Channel Transistor 有权
标题翻译：包括垂直通道晶体管的半导体存储器件
公开(公告)号：US20090189217A1
公开(公告)日：2009-07-30
申请号：US12418879
申请日：2009-04-06
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC分类号： H01L29/78
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译：半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。相邻的围绕电极围绕其中的一个柱。第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极地区。

10. 发明申请

US20080283879A1 TRANSISTOR HAVING GATE DIELECTRIC LAYER OF PARTIAL THICKNESS DIFFERENCE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：具有部分厚度差异的栅介质层的晶体管及其制造方法
公开(公告)号：US20080283879A1
公开(公告)日：2008-11-20
申请号：US12182593
申请日：2008-07-30
申请人： Byung-yong Choi , Chang-woo Oh , Dong-gun Park , Dong-won Kim
发明人： Byung-yong Choi , Chang-woo Oh , Dong-gun Park , Dong-won Kim
IPC分类号： H01L29/00
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66537 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.
摘要翻译：提供具有部分厚度差的栅极介电层的晶体管及其制造方法。该方法包括形成具有形成在半导体衬底上的较薄厚度的主要部分的栅介质层，以及形成在主体两侧的较厚厚度的侧壁部分。第一栅极形成为与栅介质层的主要部分重叠，并形成覆盖栅介质层的侧壁部分并覆盖第一栅极的第二栅极层。蚀刻第二栅极层，从而形成在第一栅极的侧壁上以间隔物形状图案化的第二栅极。使用第二栅极作为掩模来选择性地蚀刻栅极电介质层的暴露的侧壁部分，从而形成与第二栅极对准的栅极电介质层的图案。在由第二栅极暴露的半导体衬底的一部分中形成源极/漏极。

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