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1. 发明申请

US20100229072A1 APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION IN A MOBILE COMMUNICATION SYSTEM 失效
标题翻译：用于减少移动通信系统中的功耗的装置和方法
公开(公告)号：US20100229072A1
公开(公告)日：2010-09-09
申请号：US12681732
申请日：2008-10-02
申请人： Yong-Chan Kim , Il-Ho Lee
发明人： Yong-Chan Kim , Il-Ho Lee
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04H20/426 , H04H40/27 , Y02D70/1242 , Y02D70/168
摘要： An apparatus and method for reducing power consumption in a mobile communication system are provided. The apparatus includes a time slicing processor. When a frame border of the last section for determining a burst reception end time is not detected during a burst reception operation, the time slicing processor receives a burst enough to restore the whole MPE-FEC frame to the former state or receives an early burst reception end request for notifying that it is impossible to restore the whole MPE-FEC frame to the former state, and terminates the burst reception process.
摘要翻译：提供了一种用于降低移动通信系统中的功耗的装置和方法。该装置包括时间分片处理器。当在突发接收操作期间没有检测到用于确定突发接收结束时间的最后部分的帧边界时，时分片处理器接收到足以将整个MPE-FEC帧恢复到前一状态的突发或接收早期突发接收通知不可能将整个MPE-FEC帧恢复到前一状态的结束请求，并且终止突发接收处理。

2. 发明授权

US08356228B2 Apparatus and method for reducing power consumption in a mobile communication system 失效
标题翻译：用于降低移动通信系统中的功耗的装置和方法
公开(公告)号：US08356228B2
公开(公告)日：2013-01-15
申请号：US12681732
申请日：2008-10-02
申请人： Yong-Chan Kim , Il-Ho Lee
发明人： Yong-Chan Kim , Il-Ho Lee
IPC分类号： H03M13/00
CPC分类号： H04H20/426 , H04H40/27 , Y02D70/1242 , Y02D70/168
摘要： An apparatus and method for reducing power consumption in a mobile communication system are provided. The apparatus includes a time slicing processor. When a frame border of the last section for determining a burst reception end time is not detected during a burst reception operation, the time slicing processor receives a burst enough to restore the whole MPE-FEC frame to the former state or receives an early burst reception end request for notifying that it is impossible to restore the whole MPE-FEC frame to the former state, and terminates the burst reception process.
摘要翻译：提供了一种用于降低移动通信系统中的功耗的装置和方法。该装置包括时间分片处理器。当在突发接收操作期间没有检测到用于确定突发接收结束时间的最后部分的帧边界时，时分片处理器接收到足以将整个MPE-FEC帧恢复到前一状态的突发或接收早期突发接收通知不可能将整个MPE-FEC帧恢复到前一状态的结束请求，并且终止突发接收处理。

3. 发明申请

US20060026492A1 Method and apparatus for managing a deinterleaving buffer in a mobile communication system using block interleaving 审中-公开
标题翻译：用于使用块交织来管理移动通信系统中的解交织缓冲器的方法和装置
公开(公告)号：US20060026492A1
公开(公告)日：2006-02-02
申请号：US11192184
申请日：2005-07-29
申请人： Jong-Hun Rhee , Yong-Chan Kim , Su-Yean Kim , Min-Goo KIM
发明人： Jong-Hun Rhee , Yong-Chan Kim , Su-Yean Kim , Min-Goo KIM
IPC分类号： H03M13/00
CPC分类号： H03M13/2782 , H03M13/2707
摘要： A method and apparatus are provided for managing a buffer that can reduce a buffer size and a number of buffers required for a receiving stage of a mobile communication system using block interleaving. In a deinterleaving buffer configured as a plurality of sub-buffers in a receiving stage of a mobile communication system for performing Reed-Solomon (RS) decoding on frames received through a wireless network, input buffer addresses of the received frames to be input to the deinterleaving buffer, and output buffer addresses of RS-decoded frames to be output to a higher layer, are set to be cyclic by a management process. The frames input to the deinterleaving buffer are RS-decoded in a sub-buffer unit and the RS-decoded frames are output to the higher layer. Newly received frames are stored in input addresses having a same pattern with a last pattern of the output addresses in the deinterleaving buffer.
摘要翻译：提供了一种用于管理缓冲器的方法和装置，其可以使用块交织来减少移动通信系统的接收级所需的缓冲器大小和数量的缓冲器。在配置为在通过无线网络接收的帧上执行里德 - 所罗门（RS）解码的移动通信系统的接收级中的多个子缓冲器的解交织缓冲器中，输入到要输入到的帧的输入缓冲器地址解交织缓冲器和要输出到较高层的RS解码帧的输出缓冲器地址通过管理处理被设置为循环。输入到解交织缓冲器的帧以子缓冲器单元进行RS解码，并将RS解码的帧输出到较高层。新接收的帧存储在具有与解交织缓冲器中的输出地址的最后一个模式相同模式的输入地址中。

4. 发明授权

US08018021B2 Schottky diode and method of fabricating the same 有权
标题翻译：肖特基二极管及其制造方法
公开(公告)号：US08018021B2
公开(公告)日：2011-09-13
申请号：US12662452
申请日：2010-04-19
申请人： Dae-Shik Kim , Oh-Kyum Kwon , Myung-Hee Kim , Yong-Chan Kim , Hye-Young Park , Joon-Suk Oh
发明人： Dae-Shik Kim , Oh-Kyum Kwon , Myung-Hee Kim , Yong-Chan Kim , Hye-Young Park , Joon-Suk Oh
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0649 , H01L29/47 , H01L29/66143
摘要： A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction.
摘要翻译：肖特基二极管可以包括包括在半导体衬底中形成的阱和与第一阱接触的第一电极的肖特基结。该井可具有第一导电类型。第一欧姆结可以包括形成在阱中的第一结区域和与第一结区接触的第二电极。第一结区可能具有比阱更高的第一导电类型的浓度。可以在分离肖特基结和第一欧姆结的半导体衬底中形成第一器件隔离区。可以在井中形成具有与第一导电类型相反的第二导电类型的保护罩。阱护套的至少一部分可以形成在肖特基结的一部分下方。

5. 发明申请

US20080006899A1 Schottky diode and method of fabricating the same 审中-公开
标题翻译：肖特基二极管及其制造方法
公开(公告)号：US20080006899A1
公开(公告)日：2008-01-10
申请号：US11797560
申请日：2007-05-04
申请人： Dae-Shik Kim , Oh-Kyum Kwon , Myung-Hee Kim , Yong-Chan Kim , Hye-Young Park , Joon-Suk Oh
发明人： Dae-Shik Kim , Oh-Kyum Kwon , Myung-Hee Kim , Yong-Chan Kim , Hye-Young Park , Joon-Suk Oh
IPC分类号： H01L29/47 , H01L21/28
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0649 , H01L29/47 , H01L29/66143
摘要： A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may, be formed under a portion of the schottky junction.
摘要翻译：肖特基二极管可以包括包括在半导体衬底中形成的阱和与第一阱接触的第一电极的肖特基结。该井可具有第一导电类型。第一欧姆结可以包括形成在阱中的第一结区域和与第一结区接触的第二电极。第一结区可能具有比阱更高的第一导电类型的浓度。可以在分离肖特基结和第一欧姆结的半导体衬底中形成第一器件隔离区。可以在井中形成具有与第一导电类型相反的第二导电类型的保护罩。可以在肖特基结的一部分下方形成阱护罩的至少一部分。

6. 发明申请

US20060029167A1 Apparatus and method for sharing viterbi decoder in mobile communication system 审中-公开
标题翻译：用于在移动通信系统中共享维特比解码器的装置和方法
公开(公告)号：US20060029167A1
公开(公告)日：2006-02-09
申请号：US11199377
申请日：2005-08-09
申请人： Jin-Wook Han , Yong-Chan Kim
发明人： Jin-Wook Han , Yong-Chan Kim
IPC分类号： H04L27/06 , H03M13/03
CPC分类号： H03M13/6502 , H03M13/41
摘要： An apparatus and method are provided for decoding data of first and second control channels in a mobile communication system providing multi-media services including voice and data services. The apparatus includes an input section for selectively outputting data stored in first and second control channel input sections which store data of the first and second control channels, respectively, a viterbi decoder core block for outputting a decoding result by decoding the data output from the input section, an output section for storing the decoding result output from the viterbi decoder core block in one of first and second control channel output sections, and a controller for setting a second control channel delay flag, which is a signal for delaying data decoding for the second control channel, as “on” in order to perform data decoding for the first control channel if decoding start signals of the first and second control channels are simultaneously input.
摘要翻译：提供了一种用于在提供包括语音和数据服务的多媒体服务的移动通信系统中对第一和第二控制信道的数据进行解码的装置和方法。该装置包括：输入部分，用于选择性地输出存储在第一和第二控制信道输入部分中的数据，第一和第二控制信道输入部分分别存储第一和第二控制信道的数据;维特比解码器核心块，用于通过解码输入的数据来输出解码结果输出部分，用于存储从第一和第二控制信道输出部分之一的维特比解码器核心块输出的解码结果;以及控制器，用于设置第二控制信道延迟标志，该第二控制信道延迟标志是延迟数据解码的信号，第二控制信道作为“开”，以便如果解码第一和第二控制信道的开始信号被同时输入，则对第一控制信道执行数据解码。

7. 发明授权

US07961012B2 Apparatus and method for preventing generation of glitch in a clock switching circuit 有权
标题翻译：用于防止在时钟切换电路中产生毛刺的装置和方法
公开(公告)号：US07961012B2
公开(公告)日：2011-06-14
申请号：US12188277
申请日：2008-08-08
申请人： Heon-Seok Hong , Yun-Ju Kwon , Yong-Chan Kim
发明人： Heon-Seok Hong , Yun-Ju Kwon , Yong-Chan Kim
IPC分类号： H03K5/00
CPC分类号： G06F1/10
摘要： An apparatus and for preventing a glitch in a clock switching circuit includes a select signal manager and a clock gate unit. The select signal manager generates a detect change signal, provides the detect change signal as an input signal for generating a clock gate signal to the clock gate unit, and changes a muxsel signal into a select signal using the clock gate signal to select a clock intending for switching. Upon receiving the detect change signal, the clock gate unit gates a received clock, generates the clock gate signal using a level of the detect change signal as an input signal, and provides the generated clock gate signal to the select signal manager.
摘要翻译：一种用于防止时钟切换电路中的毛刺的装置包括选择信号管理器和时钟门单元。选择信号管理器生成检测改变信号，将检测改变信号提供为用于产生时钟门信号到时钟门单元的输入信号，并使用时钟门信号将多路复用器信号改变为选择信号，以选择时钟用于切换。在接收到检测变化信号时，时钟门单元对接收到的时钟进行门控，使用检测变化信号的电平作为输入信号产生时钟门信号，并将所生成的时钟门信号提供给选择信号管理器。

8. 发明授权

US07960785B2 Semiconductor integrated circuit devices 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07960785B2
公开(公告)日：2011-06-14
申请号：US12382596
申请日：2009-03-19
申请人： Yong-Don Kim , Yong-Chan Kim , Joung-Ho Kim , Mueng-Ryul Lee , Eung-Kyu Lee , Jong-Wook Lim
发明人： Yong-Don Kim , Yong-Chan Kim , Joung-Ho Kim , Mueng-Ryul Lee , Eung-Kyu Lee , Jong-Wook Lim
IPC分类号： H01L27/088
CPC分类号： H01L27/092 , H01L21/823857 , H01L21/823878 , H01L21/823892
摘要： A semiconductor integrated circuit device may include: a substrate that includes a high-voltage device region and a low-voltage device region defined on the substrate; a first buried impurity layer formed in at least a portion of the high-voltage device region and coupled to a first voltage; a second buried impurity layer formed in at least a portion of the low-voltage device region and coupled to a second voltage less than the first voltage; and a well formed on the second buried impurity layer in the low-voltage device region and coupled to a third voltage less than the second voltage.
摘要翻译：半导体集成电路器件可以包括：衬底，其包括限定在衬底上的高电压器件区域和低电压器件区域; 形成在所述高电压器件区域的至少一部分中并耦合到第一电压的第一掩埋杂质层; 第二掩埋杂质层，形成在所述低电压器件区域的至少一部分中并耦合到小于所述第一电压的第二电压; 以及在低电压器件区域中的第二掩埋杂质层上良好地形成，并且耦合到小于第二电压的第三电压。

9. 发明授权

US06504882B1 Add-compare-select circuit for viterbi decoder 失效
标题翻译：用于维特比解码器的加法比较选择电路
公开(公告)号：US06504882B1
公开(公告)日：2003-01-07
申请号：US09397756
申请日：1999-09-16
申请人： Yong-Chan Kim
发明人： Yong-Chan Kim
IPC分类号： H03D100
CPC分类号： H04L1/0059 , H03M13/093 , H03M13/4107 , H03M13/4169 , H03M13/6362 , H03M13/6516 , H04L1/0054 , H04L1/0069
摘要： There is provided a viterbi decoder for decoding convolutional data. The convolutional data includes punctured data and non punctured data. The decoder includes a branch metric unit for calculating branch metrics of the received convolutional data. An add-compare-select unit selects current and next path selection information and calculates a current state metric and a next state metric of the punctured data, from the branch metrics and a previous state metric. A traceback unit traces the current and the next path selection information selected in the add-compare-select unit to find a maximum likelihood path from which the convolutional data was received, and outputs decoded data. A controller generates a plurality of decoding control signals to the branch metric unit, the add-compare-select unit, and the traceback unit.
摘要翻译：提供了一种用于对卷积数据进行解码的维特比解码器。卷积数据包括打孔数据和非打孔数据。解码器包括用于计算接收的卷积数据的分支度量的分支度量单位。加法比较选择单元从分支度量和先前的状态度量中选择当前和下一路径选择信息并计算打孔数据的当前状态度量和下一状态度量。回溯单元跟踪在加法比较选择单元中选择的当前和下一个路径选择信息，以找到从其接收卷积数据的最大似然路径，并输出解码数据。控制器产生多个解码控制信号到分支度量单元，加法比较选择单元和回溯单元。

10. 发明授权

US06504881B1 Viterbi decoder with enhanced test function 失效
标题翻译：维特比解码器具有增强的测试功能
公开(公告)号：US06504881B1
公开(公告)日：2003-01-07
申请号：US09260381
申请日：1999-03-02
申请人： Yong-Chan Kim
发明人： Yong-Chan Kim
IPC分类号： H03M1341
CPC分类号： H03M13/6502 , H03M13/41 , H03M13/4107 , H03M13/4169
摘要： The present invention relates to an integrated viterbi decoder with improved test function. The viterbi decoder recovers original symbol and data bits from convolutional binary symbol stream, reducing a noise and data loss originated from a channel fading. For enhancing the test function of the viterbi decoder, the viterbi decoder of the present invention stores predetermined test control signals in a test register. During a test, the test control signals are synchronized with a test clock apart from a frame synchronous signal of the viterbi decoder. The test time of the viterbi decoder, thus, is not restricted by the frame synchronous signal. As a result, the test time of the viterbi decoder can be reduced without addition of an external pin.
摘要翻译：本发明涉及具有改进的测试功能的集成维特比解码器。维特比解码器从卷积二进制符号流恢复原始符号和数据位，从而减少源自信道衰落的噪声和数据丢失。为了提高维特比解码器的测试功能，本发明的维特比解码器将预定的测试控制信号存储在测试寄存器中。在测试期间，测试控制信号与除维特比解码器的帧同步信号之外的测试时钟同步。因此，维特比解码器的测试时间不受帧同步信号的限制。因此，可以减少维特比解码器的测试时间，而不需要增加外部引脚。

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