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1. 发明授权

US5311076A Tristate data output buffer having reduced switching noise and intermediate-level setting 失效
标题翻译：三态数据输出缓冲器具有降低的开关噪声和中间级设置
公开(公告)号：US5311076A
公开(公告)日：1994-05-10
申请号：US964622
申请日：1992-10-23
申请人： Yong-Bo Park , Hee-Choul Park , Hyung-Kyu Lim
发明人： Yong-Bo Park , Hee-Choul Park , Hyung-Kyu Lim
IPC分类号： G11C11/417 , G11C7/10 , G11C11/409 , H03K19/00 , H03K19/017 , H03K19/0175 , H03K19/003
CPC分类号： G11C7/1057 , G11C7/1051 , H03K19/0013 , H03K19/01728
摘要： A data output buffer suitable for use in a semiconductor memory device includes a first input circuit coupled to a first data signal and a first control signal, e.g., an output enable signal, and a second input circuit coupled to a second data signal which is the inverse of the first data signal and the first control signal. The data output buffer also includes a pull-up circuit responsive to the output of the first input circuit for selectively raising the data output node to a high voltage level, e.g., Vcc, and a pull-down circuit responsive to the output of the second input circuit for selectively lowering the data output node to a low voltage level, e.g., Vss. The data output buffer further includes a preset circuit comprised of a first preset control circuit responsive to the output of the first input circuit and a second control signal, e.g., an inverse output enable signal, for selectively raising the data output node from the low voltage level to an intermediate voltage level, e.g., 1/2 Vcc, and a second preset control circuit responsive to the output of the second input circuit and the second control signal for selectively lowering the data output node from the high voltage level to the intermediate voltage level. The preset control circuit advantageously operates to maintain the data output node at the intermediate voltage level during active states of the output enable signal without generating any DC current, thereby eliminating the noise and reliability problems of presently available data output buffers.
摘要翻译：适用于半导体存储器件的数据输出缓冲器包括耦合到第一数据信号和第一控制信号（例如，输出使能信号）的第一输入电路和耦合到第二数据信号的第二输入电路，第二数据信号是第一数据信号和第一控制信号的反相。数据输出缓冲器还包括响应于第一输入电路的输出的上拉电路，用于选择性地将数据输出节点升高到高电压电平，例如Vcc，以及响应于第二输出的输出的下拉电路输入电路，用于选择性地将数据输出节点降低到低电压电平，例如Vss。数据输出缓冲器还包括预置电路，其包括响应于第一输入电路的输出的第一预设控制电路和第二控制信号，例如反相输出使能信号，用于选择性地将数据输出节点从低电压电平到中间电压电平，例如1/2Vcc，以及响应于第二输入电路的输出和第二控制信号的第二预设控制电路，用于选择性地将数据输出节点从高电压电平降低到中间电压水平。预置控制电路有利地用于在输出使能信号的有效状态期间将数据输出节点维持在中间电压电平，而不产生任何DC电流，从而消除当前可用的数据输出缓冲器的噪声和可靠性问题。

2. 发明授权

US5396113A Electrically programmable internal power voltage generating circuit 失效
标题翻译：电可编程内部电源电压发生电路
公开(公告)号：US5396113A
公开(公告)日：1995-03-07
申请号：US922549
申请日：1992-07-31
申请人： Yong-Bo Park , Byeong-Yun Kim , Hyung-Kyu Lim
发明人： Yong-Bo Park , Byeong-Yun Kim , Hyung-Kyu Lim
IPC分类号： G11C11/413 , G05F1/56 , G11C5/14 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/50 , H03K3/01 , G11C7/00
CPC分类号： G11C5/147
摘要： An internal power voltage generating circuit of a semiconductor memory device may be constructed with a voltage sensing circuit (100) and a reference voltage controller (300) providing an internal power voltage int. V.sub.CC of a given reference voltage amplitude V.sub.ref and an external power voltage amplitude ext. V.sub.CC. Thus, when a high voltage over an operating voltage of a chip is applied to a pad (10) of the chip, the internal power voltage is raised to the level of the external power voltage. Therefore, when stress is added to the chip during a "burn-in-test", the defective chip is easily detected. Consequently, the reliability of those semiconductor memory devices subjected to post-manufacturing testing can be improved.
摘要翻译：半导体存储器件的内部电源电压产生电路可以由提供内部电源电压int的电压感测电路（100）和参考电压控制器（300）构成。给定参考电压幅值Vref的VCC和外部电源电压振幅分频。 VCC。因此，当将芯片的工作电压上的高电压施加到芯片的焊盘（10）时，内部电源电压升高到外部电源电压的电平。因此，当在“老化试验”期间将应力加到芯片上时，容易检测到有缺陷的芯片。因此，可以提高经过后期制造测试的那些半导体存储器件的可靠性。

3. 发明授权

US5349559A Internal voltage generating circuit 失效
标题翻译：内部电压发生电路
公开(公告)号：US5349559A
公开(公告)日：1994-09-20
申请号：US940205
申请日：1992-08-18
申请人： Yong-Bo Park , Hyung-Kyu Lim
发明人： Yong-Bo Park , Hyung-Kyu Lim
IPC分类号： G05F3/24 , G05F1/46 , G06F1/28 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/4074 , G11C11/413 , G11C29/00 , G11C29/06 , G11C29/50
CPC分类号： G11C5/147 , G05F1/465 , G06F1/28 , G11C11/4074 , G11C29/50 , G06F2201/81
摘要： A circuit for generating an internal voltage to be supplied to memory elements of a semiconductor memory chip during normal operation and for providing an external voltage to the memory elements during a burn-in test operation. The circuit may be constructed with a driver circuit (50) which receives an external voltage and is controlled to generate the internal voltage. A comparator (300) compares the internal voltage to a first reference voltage to produce a control signal G2 to control the driver circuit (50). An external voltage detector (100) compares a second reference voltage to the external voltage to generate control signal B2. A driver control circuit (200) is enabled by control signal B2, if the external voltage is less than the second reference voltage, to pass control signal G2 to the driver circuit and thereby enable generation of the internal voltage to be equal to, or less than, the operating voltage of the semiconductor memory chip. The driver control circuit is disabled by control signal B2 if the external voltage is greater than the second reference voltage, thereby preventing the control signal G2 of the comparator from controlling conduction by the driver circuit (50) to enable output of the external voltage exhibiting an elevated amplitude to the memory elements for burn-in test operation.
摘要翻译：一种用于在正常操作期间产生要提供给半导体存储器芯片的存储元件的内部电压并且用于在老化测试操作期间向存储器元件提供外部电压的电路。电路可以由接收外部电压的驱动电路（50）构成，并被控制以产生内部电压。比较器（300）将内部电压与第一参考电压进行比较，以产生控制信号G2以控制驱动电路（50）。外部电压检测器（100）将第二参考电压与外部电压进行比较以产生控制信号B2。如果外部电压小于第二参考电压，则通过控制信号B2使驱动器控制电路（200）启动，以将控制信号G2传递给驱动器电路，从而使内部电压的产生等于或等于或更小比半导体存储器芯片的工作电压高。如果外部电压大于第二参考电压，则控制信号B2禁止驱动器控制电路，从而防止比较器的控制信号G2控制驱动电路（50）的导通，以便能够输出外部电压升高幅度到记忆元件进行老化测试操作。

4. 发明授权

US4890051A CMOS input buffer stable for the variation of a power supplying voltage 失效
标题翻译： CMOS输入缓冲器可稳定供电电压的变化
公开(公告)号：US4890051A
公开(公告)日：1989-12-26
申请号：US289731
申请日：1988-12-27
申请人： Byung-Youn Kim , Yong-Bo Park , Tae-Sung Jung
发明人： Byung-Youn Kim , Yong-Bo Park , Tae-Sung Jung
IPC分类号： H03K19/088 , G05F3/24 , G11C11/409 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/01855 , G05F3/247
摘要： A CMOS input buffer for converting the TTL level signals to the CMOS level signals, thereby being capable of stably operating within all allowable range of the power supply voltage, is disclosed. Said CMOS input buffer includes an inverter, a reference voltage generating circuit, a power supply voltage tracer circuit and an input circuit. The input circuit includes P-channel MOS transistors and N-channel MOS transistors so as to supply a stable logic output in response to the input signal of TTL level, regardless of variation of the power supply voltage Vcc, under the control of a voltage that is approximately proportional to the difference between the reference voltage and the power supply voltage within a fixed range of the power supply voltage.
摘要翻译：公开了用于将TTL电平信号转换为CMOS电平信号的CMOS输入缓冲器，从而能够在电源电压的所有容许范围内稳定地工作。所述CMOS输入缓冲器包括反相器，参考电压产生电路，电源电压示踪器电路和输入电路。输入电路包括P沟道MOS晶体管和N沟道MOS晶体管，以便响应于TTL电平的输入信号而提供稳定的逻辑输出，而不管电源电压Vcc的变化，在电压大致与电源电压的固定范围内的参考电压和电源电压之间的差成比例。

5. 发明授权

US5067109A Data output buffer circuit for a SRAM 失效
标题翻译： SRAM的数据输出缓冲电路
公开(公告)号：US5067109A
公开(公告)日：1991-11-19
申请号：US238247
申请日：1988-08-30
申请人： Byeong-Yun Kim , Tae-Sung Jung , Yong-Bo Park
发明人： Byeong-Yun Kim , Tae-Sung Jung , Yong-Bo Park
IPC分类号： G11C11/417 , G11C7/10 , G11C11/40 , G11C11/409 , G11C11/419
CPC分类号： G11C7/1057 , G11C11/419 , G11C7/1051 , G11C7/106
摘要： For a SRAM having a sense amplifier amplifying memory data and a read/write control circuit controlling operations of the sense amplifier, a data output buffer circuit is provided, which includes: a drive output node from which data output buffer provides output data; a first circuit providing a NOR function of an SAS signal from the sense amplifier and an output enable signal (OE) from the read/write control circuit; a second circuit providing a NOR function of an SAS signal from the sense amplifier and the output enable signal (OE) from the read/write control circuit; a third circuit eliminating noise produced by transition in the outputs of the first and second circuit and also enhancing a response time; a fourth circuit inverting the output of the first circuit; a fifth circuit inverting twice, sequentially, the output of the second circuit; and a sixth circuit responsive to the fourth and fifth circuit, alternatively providing, depending on the SAS and an SAS signal from the sense amplifier, one of three states on the drive output node: a first and second output state, and a third high impedance state. None of the first, second, third, fourth, fifth, and sixth circuit requires use of a single pulse output signal externally provided to the data output buffer circuit. During transition from the first state to the second state, the drive output node passes through the third high impedance state.
摘要翻译：对于具有放大存储器数据的读出放大器的SRAM和控制读出放大器的操作的读/写控制电路，提供了一个数据输出缓冲电路，它包括：数据输出缓冲器从该驱动输出节点提供输出数据; 提供来自读出放大器的SAS信号的NOR功能和来自读/写控制电路的输出使能信号（OE）的第一电路; 提供来自读出放大器的＆upbar＆S信号的NOR功能和来自读/写控制电路的输出使能信号（OE）的第二电路; 消除由第一和第二电路的输出中的转变产生的噪声并且还增强响应时间的第三电路; 反转第一电路的输出的第四电路; 第五电路顺序地反转第二电路的输出; 以及响应于第四和第五电路的第六电路，或者根据SAS和来自读出放大器的SAS信号交替地提供驱动输出节点上的三种状态之一：第一和第二输出状态以及第三高阻抗州。第一，第二，第三，第四，第五和第六电路都不需要使用外部提供给数据输出缓冲器电路的单个脉冲输出信号。在从第一状态到第二状态的转变期间，驱动输出节点通过第三高阻抗状态。

6. 发明授权

US5051624A High speed level converter to convert a TTL logic signal to a CMOS logic signal 失效
标题翻译：高速电平转换器将TTL逻辑信号转换为CMOS逻辑信号
公开(公告)号：US5051624A
公开(公告)日：1991-09-24
申请号：US484120
申请日：1990-02-22
申请人： Yong-Bo Park
发明人： Yong-Bo Park
IPC分类号： H03K19/017 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/01721
摘要： A level converter for converting a TTL level of an input signal to a CMOS level comprises a NOR gate circuit (1), including a first voltage pull-up PMOS transistor (PI2), to which the TTL signal is inputted, an inverter (INV) connected to the NOR gate circuit, and a speed control circuit (2). The speed control circuit includes a second voltage pull-up PMOS transistor (PI4), and means are provided for connecting the first and second transistors in parallel between VCC and the input to the inverter. A fast conversion speed is obtained by turning on both PMOS transistors (PI2, PI4) when the TTL signal goes from the high level to the low level.
摘要翻译：用于将输入信号的TTL电平转换为CMOS电平的电平转换器包括NOR门电路（1），包括输入TTL信号的第一电压上拉PMOS晶体管（PI2），反相器（INV ）和速度控制电路（2）。速度控制电路包括第二电压上拉PMOS晶体管（PI4），并且提供用于在VCC和与逆变器的输入端之间并联连接第一和第二晶体管的装置。当TTL信号从高电平变为低电平时，通过接通两个PMOS晶体管（PI2，PI4）获得快速转换速度。

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