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1. 发明申请

US20100146780A1 METHOD FOR PACKAGING CIRCUITS AND PACKAGED CIRCUITS 有权
标题翻译：包装电路和包装电路的方法
公开(公告)号：US20100146780A1
公开(公告)日：2010-06-17
申请号：US12705923
申请日：2010-02-15
申请人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
发明人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
IPC分类号： H05K3/02
CPC分类号： H01L21/561 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L22/00 , H01L23/3114 , H01L24/05 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68345 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2225/06551 , H01L2225/06558 , H01L2225/06575 , H01L2924/12042 , H01L2924/14 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T29/49794 , H01L2924/00
摘要： A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.
摘要翻译：描述了一种用于封装集成电路芯片（裸片）的方法，其包括提供具有封装级触点的基底基板，用粘合剂涂覆基底基板，将模具放置在粘合剂上，将模具电连接到封装级触点，以及去除背面的基底以露出封装级触点的背面。因此，形成了基本上真正的芯片级封装。通过用密封剂填充芯片之间的间隙来形成多芯片模块。在一个实施例中，芯片通过基底衬底中的封装级触点之间的电连接互连。在一个实施例中，每个具有芯片的基板通过形成在对准的锯道中的通孔背靠背粘合以互连背对背芯片组件。

2. 发明授权

US07712211B2 Method for packaging circuits and packaged circuits 有权
标题翻译：封装电路和封装电路的方法
公开(公告)号：US07712211B2
公开(公告)日：2010-05-11
申请号：US10744632
申请日：2003-12-23
申请人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
发明人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
IPC分类号： H05K3/30
CPC分类号： H01L21/561 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L22/00 , H01L23/3114 , H01L24/05 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68345 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2225/06551 , H01L2225/06558 , H01L2225/06575 , H01L2924/12042 , H01L2924/14 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T29/49794 , H01L2924/00
摘要： A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.
摘要翻译：描述了一种用于封装集成电路芯片（裸片）的方法，其包括提供具有封装级触点的基底基板，用粘合剂涂覆基底基板，将模具放置在粘合剂上，将模具电连接到封装级触点，以及去除背面的基底以露出封装级触点的背面。因此，形成了基本上真正的芯片级封装。通过用密封剂填充芯片之间的间隙来形成多芯片模块。在一个实施例中，芯片通过基底衬底中的封装级触点之间的电连接互连。在一个实施例中，每个具有芯片的基板通过形成在对准的锯道中的通孔背靠背粘合以互连背对背芯片组件。

3. 发明授权

US08065792B2 Method for packaging circuits 有权
标题翻译：封装电路方法
公开(公告)号：US08065792B2
公开(公告)日：2011-11-29
申请号：US12705923
申请日：2010-02-15
申请人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
发明人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
IPC分类号： H05K3/20
CPC分类号： H01L21/561 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L22/00 , H01L23/3114 , H01L24/05 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68345 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2225/06551 , H01L2225/06558 , H01L2225/06575 , H01L2924/12042 , H01L2924/14 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T29/49794 , H01L2924/00
摘要： A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.
摘要翻译：描述了一种用于封装集成电路芯片（裸片）的方法，其包括提供具有封装级触点的基底基板，用粘合剂涂覆基底基板，将模具放置在粘合剂上，将模具电连接到封装级触点，以及去除背面的基底以露出封装级触点的背面。因此，形成了基本上真正的芯片级封装。通过用密封剂填充芯片之间的间隙来形成多芯片模块。在一个实施例中，芯片通过基底衬底中的封装级触点之间的电连接互连。在一个实施例中，每个具有芯片的基板通过形成在对准的锯道中的通孔背靠背粘合以互连背对背芯片组件。

4. 发明申请

US20120064697A1 METHOD FOR PACKAGING CIRCUITS 有权
标题翻译：包装电路的方法
公开(公告)号：US20120064697A1
公开(公告)日：2012-03-15
申请号：US13299120
申请日：2011-11-17
申请人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
发明人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
IPC分类号： H01L21/78
CPC分类号： H01L21/561 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L22/00 , H01L23/3114 , H01L24/05 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68345 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2225/06551 , H01L2225/06558 , H01L2225/06575 , H01L2924/12042 , H01L2924/14 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T29/49794 , H01L2924/00
摘要： A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.
摘要翻译：描述了一种用于封装集成电路芯片（裸片）的方法，其包括提供具有封装级触点的基底基板，用粘合剂涂覆基底基板，将模具放置在粘合剂上，将模具电连接到封装级触点，以及去除背面的基底以露出封装级触点的背面。因此，形成了基本上真正的芯片级封装。通过用密封剂填充芯片之间的间隙来形成多芯片模块。在一个实施例中，芯片通过基底衬底中的封装级触点之间的电连接互连。在一个实施例中，每个具有芯片的基板通过形成在对准的锯道中的通孔背靠背粘合以互连背对背芯片组件。

5. 发明授权

US08555495B2 Method for packaging circuits 有权
标题翻译：封装电路方法
公开(公告)号：US08555495B2
公开(公告)日：2013-10-15
申请号：US13299120
申请日：2011-11-17
申请人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
发明人： Yong Poo Chia , Low Siu Waf , Suan Jeung Boon , Eng Meow Koon , Swee Kwang Chua
IPC分类号： H01K3/10
CPC分类号： H01L21/561 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L22/00 , H01L23/3114 , H01L24/05 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68345 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2225/06551 , H01L2225/06558 , H01L2225/06575 , H01L2924/12042 , H01L2924/14 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T29/49794 , H01L2924/00
摘要： A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.
摘要翻译：描述了一种用于封装集成电路芯片（裸片）的方法，其包括提供具有封装级触点的基底基板，用粘合剂涂覆基底基板，将模具放置在粘合剂上，将模具电连接到封装级触点，以及去除背面的基底以露出封装级触点的背面。因此，形成了基本上真正的芯片级封装。通过用密封剂填充芯片之间的间隙来形成多芯片模块。在一个实施例中，芯片通过基底衬底中的封装级触点之间的电连接互连。在一个实施例中，每个具有芯片的基板通过形成在对准的锯道中的通孔背靠背粘合以互连背对背芯片组件。

6. 发明授权

US08564106B2 Wafer level packaging 有权
公开(公告)号：US08564106B2
公开(公告)日：2013-10-22
申请号：US13360044
申请日：2012-01-27
申请人： Swee Kwang Chua , Suan Jeung Boon , Yong Poo Chia , Yong Loo Neo
发明人： Swee Kwang Chua , Suan Jeung Boon , Yong Poo Chia , Yong Loo Neo
IPC分类号： H01L23/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/02371 , H01L2224/0401 , H01L2224/05548 , H01L2224/13024 , H01L2224/16145 , H01L2224/9202
摘要： Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.

7. 发明授权

US07485562B2 Method of making multichip wafer level packages and computing systems incorporating same 有权
标题翻译：制造多芯片晶片级封装的方法及其结合的计算系统
公开(公告)号：US07485562B2
公开(公告)日：2009-02-03
申请号：US11028374
申请日：2005-01-03
申请人： Swee Kwang Chua , Siu Waf Low , Yong Poo Chia , Meow Koon Eng , Yong Loo Neo , Suan Jeung Boon , Suangwu Huang , Wei Zhou
发明人： Swee Kwang Chua , Siu Waf Low , Yong Poo Chia , Meow Koon Eng , Yong Loo Neo , Suan Jeung Boon , Suangwu Huang , Wei Zhou
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L23/5389 , H01L21/568 , H01L23/49816 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/96 , H01L2224/05571 , H01L2224/05573 , H01L2224/12105 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H01L2924/181 , H01L2924/30107 , Y10S438/977 , H01L2924/00 , H01L2224/05599
摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.
摘要翻译：本发明定义了在芯片解决方案上提供多芯片多层系统的封装实现。实现了包含在形成在单独基板中的空腔内的多个和多种已知的良好模具的更大整合。在多芯片配置之上的附加再分布和互连层可以形成为具有终止于诸如导电凸块或球的电连接的再分布层。在一个实施例中，衬底空腔以倒装芯片配置接收多个半导体晶片的信号器件连接，例如导电凸块。然后将衬底的背面的一部分去除足以露出导电凸块的深度。在另一个实施例中，空腔容纳半导体晶片，其有源表面朝上，其中形成金属层连接并耦合到半导体晶片的接合焊盘或其它电连接器。还公开了包含包装的计算系统。

8. 发明授权

US07274094B2 Leadless packaging for image sensor devices 有权
标题翻译：图像传感器设备无引线封装
公开(公告)号：US07274094B2
公开(公告)日：2007-09-25
申请号：US10233319
申请日：2002-08-28
申请人： Suan Jeung Boon , Yong Poo Chia , Yong Loo Neo , Swee Kwang Chua , Siu Waf Low
发明人： Suan Jeung Boon , Yong Poo Chia , Yong Loo Neo , Swee Kwang Chua , Siu Waf Low
IPC分类号： H01L23/495
CPC分类号： H01L31/0203 , H01L2224/16245
摘要： A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.
摘要翻译：无引线图像传感器封装及其组装方法。在第一实施例中，图像传感器芯片以倒装芯片方式安装在封装外壳的底侧空腔内，使得图像传感器芯片上的感测电路通过封装壳体的顶侧中的孔露出。透明的密封剂材料沉积在孔内以包围封装外壳和图像传感器芯片之间的互连结。透明盖通过密封剂材料保持在孔的适当位置。图像传感器芯片的背面被暴露。在特别适用于高端图像传感器的第二实施例中，不需要密封材料。相反，背盖被密封到封装壳体中的凸缘表面以覆盖底侧空腔。形成在背盖上的压缩构件与图像传感器芯片接触并保持互连接合完整性。

9. 发明申请

US20120119263A1 WAFER LEVEL PACKAGING 有权
标题翻译：水平包装
公开(公告)号：US20120119263A1
公开(公告)日：2012-05-17
申请号：US13360044
申请日：2012-01-27
申请人： Swee Kwang Chua , Suan Jeung Boon , Yong Poo Chia , Yong Loo Neo
发明人： Swee Kwang Chua , Suan Jeung Boon , Yong Poo Chia , Yong Loo Neo
IPC分类号： H01L23/52
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/02371 , H01L2224/0401 , H01L2224/05548 , H01L2224/13024 , H01L2224/16145 , H01L2224/9202
摘要： Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.
摘要翻译：通过在衬底的顶侧中形成沟槽和在衬底的后侧中的至少一个沟槽来形成衬底中的通孔。沟槽的深度之和至少等于基板的高度。沟槽在交叉路口处交叉，这相应地形成从顶侧到后侧的通孔。通孔填充有导体，以在基板的两侧和边缘上形成接触。在每个沟槽上形成背面的触点。通孔从边缘接触。跟踪将连接焊盘连接到通孔中的导体。一些痕迹平行于背面痕迹。一些痕迹偏向背面痕迹。将基底切成单个模具。

10. 发明授权

US08106488B2 Wafer level packaging 有权
标题翻译：晶圆级包装
公开(公告)号：US08106488B2
公开(公告)日：2012-01-31
申请号：US12898896
申请日：2010-10-06
申请人： Swee Kwang Chua , Suan Jeung Boon , Yong Poo Chia , Neo Yong Loo
发明人： Swee Kwang Chua , Suan Jeung Boon , Yong Poo Chia , Neo Yong Loo
IPC分类号： H01L39/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/02371 , H01L2224/0401 , H01L2224/05548 , H01L2224/13024 , H01L2224/16145 , H01L2224/9202
摘要： Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.
摘要翻译：通过在衬底的顶侧中形成沟槽和在衬底的后侧中的至少一个沟槽来形成衬底中的通孔。沟槽的深度之和至少等于基板的高度。沟槽在交叉路口处交叉，这相应地形成从顶侧到后侧的通孔。通孔填充有导体，以在基板的两侧和边缘上形成接触。在每个沟槽上形成背面的触点。通孔从边缘接触。跟踪将连接焊盘连接到通孔中的导体。一些痕迹平行于背面痕迹。一些痕迹偏向背面痕迹。将基底切成单个模具。

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