专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07966581B2 Generic non-volatile service layer 有权
标题翻译：通用非易失性服务层
公开(公告)号：US07966581B2
公开(公告)日：2011-06-21
申请号：US12252564
申请日：2008-10-16
申请人： Yiran Chen , Dadi Setiadi , Hai Li , Haiwen Xi , Hongyue Liu
发明人： Yiran Chen , Dadi Setiadi , Hai Li , Haiwen Xi , Hongyue Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.
摘要翻译：在电子设备中构建和操作集成电路的方法和装置。在一些实施例中，通用服务层集成在三维集成电路中，并使用存储在非易失性存储器中的测试模式进行测试。通用服务层被重新配置为集成电路的永久性非测试功能组件。

2. 发明申请

US20100100857A1 GENERIC NON-VOLATILE SERVICE LAYER 有权
标题翻译：一般非易失性服务层
公开(公告)号：US20100100857A1
公开(公告)日：2010-04-22
申请号：US12252564
申请日：2008-10-16
申请人： Yiran Chen , Dadi Setiadi , Hai Li , Haiwen Xi , Hongyue Liu
发明人： Yiran Chen , Dadi Setiadi , Hai Li , Haiwen Xi , Hongyue Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.
摘要翻译：在电子设备中构建和操作集成电路的方法和装置。在一些实施例中，通用服务层集成在三维集成电路中，并使用存储在非易失性存储器中的测试模式进行测试。通用服务层被重新配置为集成电路的永久性非测试功能组件。

3. 发明申请

US20110007588A1 Defective Bit Scheme for Multi-Layer Integrated Memory Device 有权
标题翻译：多层集成存储器件缺陷位方案
公开(公告)号：US20110007588A1
公开(公告)日：2011-01-13
申请号：US12502194
申请日：2009-07-13
申请人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
发明人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
IPC分类号： G11C29/00 , G11C29/04 , G11C15/00
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C29/44 , G11C29/808 , G11C2029/0403
摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
摘要翻译：本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

4. 发明授权

US07936622B2 Defective bit scheme for multi-layer integrated memory device 有权
标题翻译：多层集成存储器件的不良位方案
公开(公告)号：US07936622B2
公开(公告)日：2011-05-03
申请号：US12502194
申请日：2009-07-13
申请人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
发明人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
IPC分类号： G11C29/00
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C29/44 , G11C29/808 , G11C2029/0403
摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
摘要翻译：本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

5. 发明申请

US20100037020A1 PIPELINED MEMORY ACCESS METHOD AND ARCHITECTURE THEREFORE 审中-公开
标题翻译：管道存储器访问方法和架构
公开(公告)号：US20100037020A1
公开(公告)日：2010-02-11
申请号：US12200118
申请日：2008-08-28
申请人： Hai Li , Yiran Chen , Hongyue Liu , Dadi Setiadi , Brian Lee
发明人： Hai Li , Yiran Chen , Hongyue Liu , Dadi Setiadi , Brian Lee
IPC分类号： G06F12/00
CPC分类号： G11C7/1039 , G11C8/10 , G11C8/18
摘要： A memory array and a method for accessing a memory array including: receiving an address from a host related to relevant data; accessing a first module based on the address received from the host, wherein accessing the first module includes: decoding the address for the first module; enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module; and outputting information regarding the first module; and accessing a second module based on the address received from the host, wherein accessing the second module includes: decoding the address for the second module; enabling a wordline based on the decoded address for the second module and sensing the contents of one or more bits at the decoded address for the second module; and outputting information regarding the second module, wherein the step of decoding the address for the second module occurs while the step of enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module occurs.
摘要翻译：一种用于访问存储器阵列的存储器阵列和方法，包括：从相关数据相关的主机接收地址; 基于从所述主机接收的地址访问第一模块，其中访问所述第一模块包括：解码所述第一模块的地址; 基于第一模块的解码地址启用字线，并感测第一模块的解码地址处的一个或多个位的内容; 并输出关于第一模块的信息; 以及基于从所述主机接收的地址访问第二模块，其中访问所述第二模块包括：对所述第二模块的地址进行解码; 基于第二模块的解码地址启用字线，并感测第二模块的解码地址处的一个或多个位的内容; 以及输出关于第二模块的信息，其中对第二模块的地址进行解码的步骤在基于第一模块的解码地址启用字线的步骤并且感测解码地址处的一个或多个位的内容的步骤第一个模块发生。

6. 发明申请

US20090289736A1 MAGNETIC SWITCHES FOR SPINWAVE TRANSMISSION 审中-公开
标题翻译：用于旋转传动的磁力开关
公开(公告)号：US20090289736A1
公开(公告)日：2009-11-26
申请号：US12125974
申请日：2008-05-23
申请人： Haiwen Xi , Dadi Setiadi , Insik Jin , Yang Li , Song Xue
发明人： Haiwen Xi , Dadi Setiadi , Insik Jin , Yang Li , Song Xue
IPC分类号： H01P1/10 , H01H53/00
CPC分类号： H01H59/0009 , H01H57/00
摘要： Spinwave transmission systems that include switching devices to direct the transmission of the spinwaves used for data transfer and processing. In one particular embodiment, a system for spinwave transmission has a first magnetic stripe configured for transmission of a spinwave and a second magnetic stripe for transmission of the spinwave, with a gap therebetween. The system includes a coupler that has a first orientation and a second orientation, where in the first orientation, no magnetic connection is made between the magnetic stripes, and in the second orientation, a connection is made between the magnetic stripes. The connection allows transmission of the spinwave from the first magnetic stripe to the second magnetic stripe. The first and second orientation may be the physical position of the coupler, moved by thermal, piezoelectric, or electrostatic forces, or, the first and second orientation may be a magnetic state of the coupler.
摘要翻译：旋转波传输系统包括用于引导用于数据传输和处理的旋转波的传输的开关装置。在一个具体实施例中，用于旋转波传输的系统具有被配置为用于传输旋转波的第一磁条和用于传播旋转波的第二磁条，其间具有间隙。该系统包括具有第一取向和第二取向的耦合器，其中在第一取向中，在磁条之间不形成磁连接，并且在第二取向中，在磁条之间形成连接。该连接允许将旋转波从第一磁条传输到第二磁条。第一和第二取向可以是耦合器的物理位置，通过热，压电或静电力移动，或者第一和第二取向可以是耦合器的磁状态。

7. 发明申请

US20100104115A1 MICRO MAGNETIC SPEAKER DEVICE WITH BALANCED MEMBRANE 审中-公开
标题翻译：具有平衡膜的微型磁性扬声器装置
公开(公告)号：US20100104115A1
公开(公告)日：2010-04-29
申请号：US12361905
申请日：2009-01-29
申请人： Jun Zheng , Dadi Setiadi , Haiwen Xi , Insik Jin , Nurul Amin
发明人： Jun Zheng , Dadi Setiadi , Haiwen Xi , Insik Jin , Nurul Amin
IPC分类号： H04R25/00 , H04R1/00
CPC分类号： H04R1/00
摘要： A micro magnetic device with a micro magnetic speaker unit having a first element, a second element, and a membrane therebetween. Each of the elements comprises a body, a pole of soft magnetic material, an electrically conductive coil positioned around the pole, and a permanent magnet connected to the membrane. The first element and the second element are magnetically identical. A plurality of speaker units can be combined to provide a speaker array.
摘要翻译：具有微型磁性扬声器单元的微型磁性装置具有第一元件，第二元件和它们之间的隔膜。每个元件包括主体，软磁材料的极，围绕极的定位的导电线圈和连接到膜的永磁体。第一元件和第二元件是磁性相同的。可以组合多个扬声器单元以提供扬声器阵列。

8. 发明申请

US20100140790A1 CHIP HAVING THERMAL VIAS AND SPREADERS OF CVD DIAMOND 审中-公开
标题翻译：具有CVD金刚石的热水和散热片的芯片
公开(公告)号：US20100140790A1
公开(公告)日：2010-06-10
申请号：US12500268
申请日：2009-07-09
申请人： Dadi Setiadi , Hongyue Liu
发明人： Dadi Setiadi , Hongyue Liu
IPC分类号： H01L23/373 , H01L23/48 , H01L23/52
CPC分类号： H05K1/0206 , H01L23/3677 , H01L23/3732 , H01L23/49551 , H01L24/48 , H01L25/0657 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/06589 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/1305 , H01L2924/14 , H01L2924/181 , H05K3/42 , H05K2201/10689 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit chip having a heat spreader comprising CVD diamond extending along the chip support body and thermal vias extending through the support body in regions free of active devices or functional elements. The thermal vias may thermally conductive and electrically conductive or may be thermally conductive and electrically resistive. The integrated circuit chips may be 3D integrated circuit chips.
摘要翻译：一种具有散热器的集成电路芯片，其包括沿着芯片支撑体延伸的CVD金刚石和在没有有源器件或功能元件的区域中延伸穿过支撑体的热通孔。热通孔可以是导热的和导电的，或者可以是导热的和电阻的。集成电路芯片可以是3D集成电路芯片。

9. 发明申请

US20110007597A1 Semiconductor Control Line Address Decoding Circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US20110007597A1
公开(公告)日：2011-01-13
申请号：US12502219
申请日：2009-07-13
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

10. 发明申请

US20100302849A1 NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE 有权
标题翻译：具有集成位线电容的NAND闪存
公开(公告)号：US20100302849A1
公开(公告)日：2010-12-02
申请号：US12474463
申请日：2009-05-29
申请人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
发明人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C11/005 , G11C16/26 , G11C2216/14
摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
摘要翻译：用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。在一些实施例中，易失性存储器单元是来自所述单元的行的动态随机存取存储器（DRAM）单元，其中每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元包括以NAND配置连接的闪存单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式