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1. 发明授权

US06593244B1 Process for etching conductors at high etch rates 失效
标题翻译：以高蚀刻速率蚀刻导体的工艺
公开(公告)号：US06593244B1
公开(公告)日：2003-07-15
申请号：US09659072
申请日：2000-09-11
申请人： Yiqiong Wang , Anisul Khan , Ajay Kumar , Dragan Podlesnik , Sharma V. Pamarthy
发明人： Yiqiong Wang , Anisul Khan , Ajay Kumar , Dragan Podlesnik , Sharma V. Pamarthy
IPC分类号： H01L21302
CPC分类号： C23F4/00 , H01L21/02071 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： A process for etching a pattern-masked conductor substrate anisotropically so as to obtain very high etch rates comprising adding a polymer-forming fluorocarbon gas and an etch gas at high flow rates to an etch chamber at etching pressures of 77 millitorr to 100 Torr using a high source power and bias power to the substrate support electrode to form a high density plasma. The gases can be added together, sequentially or alternately.
摘要翻译：一种用于各向异性蚀刻图案掩模的导体衬底以便获得非常高的蚀刻速率的方法，包括以77毫微伏至100托的蚀刻压力，将高聚物形成碳氟化合物气体和蚀刻气体以高流速加入蚀刻室，高源功率和偏置功率到衬底支撑电极以形成高密度等离子体。气体可以一起，依次或交替地加入。

2. 发明授权

US06897155B2 Method for etching high-aspect-ratio features 失效
标题翻译：蚀刻高纵横比特征的方法
公开(公告)号：US06897155B2
公开(公告)日：2005-05-24
申请号：US10219885
申请日：2002-08-14
申请人： Ajay Kumar , Anisul H. Khan , Dragan Podlesnik , Sharma V. Pamarthy , Axel Henke , Stephan Wege , Virinder Grewal
发明人： Ajay Kumar , Anisul H. Khan , Dragan Podlesnik , Sharma V. Pamarthy , Axel Henke , Stephan Wege , Virinder Grewal
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/461
CPC分类号： H01J37/32082 , H01J2237/3347 , H01L21/3065 , H01L21/30655
摘要： A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.
摘要翻译：一种用于操作等离子体反应器以蚀刻真空室中的工件上的高纵横比特征的方法。该方法包括执行闪光处理之后的蚀刻工艺。在蚀刻工艺期间，将第一气体供应到真空室中，并且第一气体的等离子体保持第一时间段。第一气体的等离子体包括蚀刻剂和钝化物质。在闪蒸过程中，将包含沉积物去除气体的第二气体供应到真空室中，并且将第二气体的等离子体保持第二时间段。在第二时间段期间，工件与第二气体的等离子体之间的直流电压明显小于在第一时间段内第一气体的工件和等离子体之间的直流电压。

3. 发明授权

US06827869B2 Method of micromachining a multi-part cavity 失效
标题翻译：微加工多部分腔体的方法
公开(公告)号：US06827869B2
公开(公告)日：2004-12-07
申请号：US10194167
申请日：2002-07-11
申请人： Dragan Podlesnik , Thorsten Lill , Jeff Chinn , Shaoher X. Pan , Anisul Khan , Maocheng Li , Yiqiong Wang
发明人： Dragan Podlesnik , Thorsten Lill , Jeff Chinn , Shaoher X. Pan , Anisul Khan , Maocheng Li , Yiqiong Wang
IPC分类号： H01L21302
CPC分类号： H01L27/1087 , B81B2201/052 , B81B2203/0315 , B81B2203/033 , B81C1/00119 , B81C2201/016 , H01L21/3065 , H01L21/3086
摘要： The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes. The method is also useful whenever it is necessary to maintain tight control over the dimensions of the shaped opening.
摘要翻译：本公开涉及我们发现用于蚀刻衬底中的多部分空腔的特别有效的方法。该方法提供了首先蚀刻成形开口，在成形开口的内表面的至少一部分上沉积保护层，然后直接在成形开口下面蚀刻成形腔，并与成形开口连续连通。保护层在蚀刻成形腔体期间保护成形开口的蚀刻轮廓，从而如果需要，成形开口和成形腔体可以被蚀刻以具有不同的形状。在本发明方法的特定实施例中，横向蚀刻阻挡层和/或注入的蚀刻停止点也用于引导蚀刻工艺。本发明的方法可以应用于需要或期望提供具有不同形状的成形开口和下面的成形腔的任何应用。只要需要对成形开口的尺寸进行严格控制，该方法也是有用的。

4. 发明授权

US06380095B1 Silicon trench etch using silicon-containing precursors to reduce or avoid mask erosion 失效
标题翻译：使用含硅前体进行硅沟槽蚀刻，以减少或避免掩模侵蚀
公开(公告)号：US06380095B1
公开(公告)日：2002-04-30
申请号：US09716074
申请日：2000-11-16
申请人： Wei Liu , Yiqiong Wang , Maocheng Li , Anisul Khan , Shaoher Pan , Dragan Podlesnik
发明人： Wei Liu , Yiqiong Wang , Maocheng Li , Anisul Khan , Shaoher Pan , Dragan Podlesnik
IPC分类号： H01L21302
CPC分类号： H01L21/3065
摘要： The present invention pertains to an etch chemistry and method useful for the etching of silicon surfaces. The method is particularly useful in the deep trench etching of silicon where profile control is important. In the case of deep trench etching, at least a portion of the substrate toward the bottom of the trench is etched using a combination of reactive gases including a fluorine-containing compound which does not contain silicon (FC); a silicon-containing compound (SC) which does not contain fluorine; and oxygen (O2).
摘要翻译：本发明涉及用于蚀刻硅表面的蚀刻化学和方法。该方法在硅的深沟槽蚀刻中特别有用，其中轮廓控制是重要的。在深沟槽蚀刻的情况下，使用包含不含硅（FC）的含氟化合物的反应性气体的组合来蚀刻朝向沟槽底部的至少一部分衬底; 不含氟的含硅化合物（SC）; 和氧气（O2）。

5. 发明授权

US06270634B1 Method for plasma etching at a high etch rate 失效
标题翻译：用于以高蚀刻速率进行等离子体蚀刻的方法
公开(公告)号：US06270634B1
公开(公告)日：2001-08-07
申请号：US09430798
申请日：1999-10-29
申请人： Ajay Kumar , Anisul Khan , Jeffrey D Chinn , Dragan Podlesnik
发明人： Ajay Kumar , Anisul Khan , Jeffrey D Chinn , Dragan Podlesnik
IPC分类号： C23C1434
CPC分类号： H01L21/67069 , H01J37/321 , H01J37/32935 , H01L21/3065
摘要： This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched. In the second step, a low etch rate process having an etch rate below about two microns per minute is used to remove any residual material not removed by the first etch step.
摘要翻译：本发明涉及用于快速等离子体蚀刻难以高速蚀刻的材料的方法。该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。该方法包括使用包括蚀刻剂气体和溅射气体的等离子体源气体。在蚀刻工艺中使用两个单独的电源，并且可以有利地调整蚀刻剂气体和溅射气体的流量之间的比例，以获得大于每分钟2微米的氮化硅的蚀刻速率。另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。两步法的第一蚀刻步骤提供了每分钟约2微米的高蚀刻速率，以便基本上除去所有待蚀刻的层。在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺来去除通过第一蚀刻步骤未被去除的任何残留材料。

6. 发明授权

US06518192B2 Two etchant etch method 失效
公开(公告)号：US06518192B2
公开(公告)日：2003-02-11
申请号：US10013115
申请日：2001-12-07
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.

7. 发明授权

US06391788B1 Two etchant etch method 失效
标题翻译：两种蚀刻剂蚀刻方法
公开(公告)号：US06391788B1
公开(公告)日：2002-05-21
申请号：US09513552
申请日：2000-02-25
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.
摘要翻译：描述了用于蚀刻作为掩模结构的一部分的层的两种蚀刻剂蚀刻方法。该方法例如在微电机械系统（MEMS）应用中以及集成电路和其它电子设备的制造中是有用的。该方法可以有利地用于优化等离子体蚀刻工艺，该等离子体蚀刻工艺能够蚀刻具有89°+/- 1°侧壁的严格轮廓控制沟槽，该硅层形成为掩模结构的一部分，其中掩模结构引起蚀刻速率的变化。本发明的两种蚀刻剂蚀刻方法蚀刻具有第一蚀刻剂蚀刻的结构中的层，直到蚀刻最快蚀刻区域中的层。然后用第二蚀刻剂蚀刻该层，直到蚀刻具有最慢蚀刻速率的区域中的层。还可以选择第二蚀刻剂以向结构的下层提供侧壁钝化和选择性。

8. 发明授权

US06372655B2 Two etchant etch method 失效
公开(公告)号：US06372655B2
公开(公告)日：2002-04-16
申请号：US09836934
申请日：2001-04-17
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , B81B2203/033 , B81C1/00571 , B81C2201/0132 , H01L21/3065 , H01L21/32137
摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

9. 发明授权

US06802933B2 Apparatus for performing self cleaning method of forming deep trenches in silicon substrates 失效
标题翻译：用于在硅衬底中形成深沟槽的自清洁方法的装置
公开(公告)号：US06802933B2
公开(公告)日：2004-10-12
申请号：US09740146
申请日：2000-12-18
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： C23F100
CPC分类号： H01L21/67069 , H01L21/3065 , H01L21/76232 , H01L27/1087 , Y10S156/916
摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.
摘要翻译：本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

10. 发明授权

US06318384B1 Self cleaning method of forming deep trenches in silicon substrates 失效
标题翻译：在硅衬底中形成深沟槽的自清洗方法
公开(公告)号：US06318384B1
公开(公告)日：2001-11-20
申请号：US09405349
申请日：1999-09-24
申请人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Anisul Khan , Ajay Kumar , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L21302
CPC分类号： H01L21/67069 , H01L21/3065 , H01L21/76232 , H01L27/1087 , Y10S156/916
摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.
摘要翻译：本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

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