专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08036044B2 Dynamically adjustable erase and program levels for non-volatile memory 有权
标题翻译：用于非易失性存储器的动态可调擦除和程序级别
公开(公告)号：US08036044B2
公开(公告)日：2011-10-11
申请号：US12504576
申请日：2009-07-16
申请人： Yingda Dong , Jun Wan
发明人： Yingda Dong , Jun Wan
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/344 , G11C16/16
摘要： Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided.
摘要翻译：通过自适应地调整擦除验证级别和程序验证级别来降低非易失性存储元件的降级。确定完成擦除操作所需的擦除脉冲数或最高擦除脉冲幅度。当数字或幅度达到极限时，擦除验证电平增加。随着擦除验证电平的增加，所需擦除脉冲的数量减少，因为擦除操作可以更容易地完成。从而避免了退化的加速增加。一个或多个程序验证级别也可以随着擦除验证级别的变化而增加。一个或多个程序验证电平可以增加与擦除验证电平相同的增量，以在擦除状态和编程状态之间维持恒定的阈值电压窗口，或者通过不同的增量。提供了具有二进制或多级存储元素的实现。

2. 发明申请

US20110013460A1 DYNAMICALLY ADJUSTABLE ERASE AND PROGRAM LEVELS FOR NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的动态可调删除和程序级别
公开(公告)号：US20110013460A1
公开(公告)日：2011-01-20
申请号：US12504576
申请日：2009-07-16
申请人： Yingda Dong , Jun Wan
发明人： Yingda Dong , Jun Wan
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/344 , G11C16/16
摘要： Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided.
摘要翻译：通过自适应地调整擦除验证级别和程序验证级别来降低非易失性存储元件的降级。确定完成擦除操作所需的擦除脉冲数或最高擦除脉冲幅度。当数字或幅度达到极限时，擦除验证电平增加。随着擦除验证电平的增加，所需擦除脉冲的数量减少，因为擦除操作可以更容易地完成。从而避免了退化的加速增加。一个或多个程序验证级别也可以随着擦除验证级别的变化而增加。一个或多个程序验证电平可以增加与擦除验证电平相同的增量，以在擦除状态和编程状态之间维持恒定的阈值电压窗口，或者通过不同的增量。提供了具有二进制或多级存储元素的实现。

3. 发明授权

US08472257B2 Nonvolatile memory and method for improved programming with reduced verify 有权
标题翻译：非易失性存储器和方法，通过减少验证来改进编程
公开(公告)号：US08472257B2
公开(公告)日：2013-06-25
申请号：US13071170
申请日：2011-03-24
申请人： Yingda Dong , Ken Oowada , Cynthia Hsu
发明人： Yingda Dong , Ken Oowada , Cynthia Hsu
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/10 , G11C16/3468
摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
摘要翻译：非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。存储器状态由一组增加的分界阈值（V1，...，VN）划分。最初在编程过程中，相对于测试参考阈值验证存储器单元。该测试参考阈值具有超过设定中的指定分界阈值Vi的值偏移预定余量。可以确定当经过Vi编程时每个存储单元的过冲大于或小于余量。因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

4. 发明申请

US20120314499A1 INTELLIGENT SHIFTING OF READ PASS VOLTAGES FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储器的读取电压的智能转换
公开(公告)号：US20120314499A1
公开(公告)日：2012-12-13
申请号：US13155323
申请日：2011-06-07
申请人： Jiahui Yuan , Yingda Dong , Charles Kwong
发明人： Jiahui Yuan , Yingda Dong , Charles Kwong
IPC分类号： G11C16/26 , G11C16/06 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3454 , G11C16/349 , G11C29/021 , G11C29/028
摘要： A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage.
摘要翻译：确定并优化循环存储器的第一个读通过电压。为一个或多个管芯确定一个或多个启动读通过电压。该系统基于编程/擦除擦除周期的数量，第一读取通过电压和相应的启动读取通过电压来动态地计算当前的读取通过电压。使用计算出的电流读通过电压从一个或多个非易失性存储元件读取数据。

5. 发明授权

US08144511B2 Selective memory cell program and erase 有权
公开(公告)号：US08144511B2
公开(公告)日：2012-03-27
申请号：US12544113
申请日：2009-08-19
申请人： Yingda Dong , Tien-chien Kuo , Gerrit Jan Hemink
发明人： Yingda Dong , Tien-chien Kuo , Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3418 , G11C2211/5641
摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

6. 发明授权

US08081514B2 Partial speed and full speed programming for non-volatile memory using floating bit lines 有权
标题翻译：使用浮动位线对非易失性存储器进行部分速度和全速编程
公开(公告)号：US08081514B2
公开(公告)日：2011-12-20
申请号：US12547449
申请日：2009-08-25
申请人： Man Mui , Yingda Dong , Binh Lee , Deepanshu Dutta
发明人： Man Mui , Yingda Dong , Binh Lee , Deepanshu Dutta
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.
摘要翻译：非易失性存储器系统实现了部分速度和全速编程。在编程操作期间，在第一时间段中，要禁止的存储元件的位线被预充电，而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线是固定的在第二时间段中，以部分速度编程的存储元件的位线被驱动得较高，而待禁止的存储元件的位线被浮置，并且待编程的存储元件的位线保持固定。在第三时间段中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

7. 发明申请

US20110249504A1 SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY 有权
标题翻译：存储器中程序噪声减少的SAW形状多脉冲编程
公开(公告)号：US20110249504A1
公开(公告)日：2011-10-13
申请号：US12757399
申请日：2010-04-09
申请人： Yingda Dong , Yupin K. Fong , Gerrit Jan Hemink
发明人： Yingda Dong , Yupin K. Fong , Gerrit Jan Hemink
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C2211/5621 , G11C2211/5622
摘要： In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.
摘要翻译：在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。该集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。在子脉冲组之后执行验证操作。每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。

8. 发明授权

US07995394B2 Program voltage compensation with word line bias change to suppress charge trapping in memory 有权
标题翻译：程序电压补偿用字线偏置改变，以抑制存储器中的电荷捕获
公开(公告)号：US07995394B2
公开(公告)日：2011-08-09
申请号：US12512181
申请日：2009-07-30
申请人： Yingda Dong , Toru Ishigaki , Ken Oowada
发明人： Yingda Dong , Toru Ishigaki , Ken Oowada
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3404
摘要： Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage.
摘要翻译：在所选择的字线的编程操作期间，在非易失性存储系统中，通过在与所选择的字线相邻的字线上最初使用具有较低幅度的通过电压来减少编程干扰。这有助于减少浮栅边缘的电荷捕获，这可以通过增加编程擦除周期来扩大阈值电压分布。当将较高幅度的编程脉冲施加到所选字线时，通过电压切换到较高电平以提供足够量的通道升压。可以通过施加指定的编程脉冲或者通过跟踪下部状态存储元件直到达到目标验证电平来触发切换到较高通过电压。当通过电压升高时，编程电压的幅度降低，从通过电压的变化中消除所选存储元件的电容耦合。

9. 发明申请

US20100329010A1 READ OPERATION FOR MEMORY WITH COMPENSATION FOR COUPLING BASED ON WRITE-ERASE CYCLES 有权
标题翻译：用于基于写删除循环的耦合补偿的存储器的读操作
公开(公告)号：US20100329010A1
公开(公告)日：2010-12-30
申请号：US12490550
申请日：2009-06-24
申请人： Yingda Dong
发明人： Yingda Dong
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483
摘要： A read operation for non-storage elements compensates for floating gate-to-floating gate coupling and effects of program-erase cycles. During programming of a word line WLn+1, the threshold voltages of previously-programmed storage elements on WLn are increased due to coupling. To compensate for the increase, during a subsequent read operation of WLn, different sets of pass voltages are applied to WLn+1 for each control gate read voltage which is applied to WLn. The pass voltages vary in each different set so that they are a function of the control gate read voltage which is applied to WLn. The pass voltages may also be a function of a number of program-erase cycles. A higher amount of compensation is provided by increasing the pass voltages as the number of program-erase cycles increases.
摘要翻译：非存储元件的读操作补偿浮置栅极与浮置栅极耦合以及编程擦除周期的影响。在字线WLn + 1的编程期间，WLn上预先编程的存储元件的阈值电压由于耦合而增加。为了补偿增加，在WLn的后续读取操作期间，对施加到WLn的每个控制栅极读取电压，向WLn + 1施加不同的通过电压集合。通过电压在每个不同的组中变化，使得它们是施加到WLn的控制栅极读取电压的函数。通过电压也可以是编程擦除周期数的函数。当编程擦除周期数增加时，通过增加通过电压来提供更高的补偿量。

10. 发明授权

US07800956B2 Programming algorithm to reduce disturb with minimal extra time penalty 有权
标题翻译：编程算法以最小的额外时间损失来减少干扰
公开(公告)号：US07800956B2
公开(公告)日：2010-09-21
申请号：US12163073
申请日：2008-06-27
申请人： Dana Lee , Deepanshu Dutta , Yingda Dong
发明人： Dana Lee , Deepanshu Dutta , Yingda Dong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多遍编程过程中，非易失性存储器中的编程时间会减少。在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式