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1. 发明申请

US20140006883A1 SYSTEM AND METHOD FOR ALIGNING DATA BITS 有权
标题翻译：用于对准数据位的系统和方法
公开(公告)号：US20140006883A1
公开(公告)日：2014-01-02
申请号：US13539519
申请日：2012-07-02
申请人： Ying-Yu HSU , Ruey-Bin SHEEN , Shih-Hung LAN , Chih-Hsien CHANG
发明人： Ying-Yu HSU , Ruey-Bin SHEEN , Shih-Hung LAN , Chih-Hsien CHANG
IPC分类号： G06F11/07
CPC分类号： H04L25/14 , G06F13/1689
摘要： Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.
摘要翻译：公开了通过调整这些数据位的输入线的定时来对准多个数据位的系统和方法。实施例包括用于比较多组位的定时的分层结构。其他实施例包括在3D管芯堆叠架构中对准来自多个芯片的数据位。

2. 发明申请

US20130038366A1 BIST CIRCUIT FOR PHASE MEASUREMENT 有权
标题翻译：用于相位测量的BIST电路
公开(公告)号：US20130038366A1
公开(公告)日：2013-02-14
申请号：US13205722
申请日：2011-08-09
申请人： Tsung-Hsien TSAI , Min-Shueh YUAN , Chih-Hsien CHANG
发明人： Tsung-Hsien TSAI , Min-Shueh YUAN , Chih-Hsien CHANG
IPC分类号： H03K19/00 , H03L7/06
CPC分类号： G01R31/3016 , G01R31/31725 , G01R31/31726 , G01R31/31727 , G01R31/3187
摘要： A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.
摘要翻译：用于高速应用的BIST电路包括相位差检测电路，具有耦合到相位差检测电路的输出的输入的周期到电流转换电路和耦合到该相位差检测电路的输出的电流 - 电压转换电路周期到电流转换电路。相位差检测电路包括用于接收输入时钟信号和输入时钟信号的反相版本的延迟版本作为输入的第一NAND逻辑; 用于接收输入时钟信号的反相版本和输入时钟信号的延迟版本的第二NAND逻辑; 用于接收输入时钟信号和输入时钟信号的延迟版本作为输入的第三NAND逻辑; 以及用于接收输入时钟信号的反相版本和输入时钟信号的反相版本的延迟版本的第四NAND逻辑。

3. 发明申请

US20130311957A1 SEMICONDUCTOR DEVICE DESIGN SYSTEM AND METHOD OF USING THE SAME 有权
标题翻译：半导体器件设计系统及其使用方法
公开(公告)号：US20130311957A1
公开(公告)日：2013-11-21
申请号：US13475853
申请日：2012-05-18
申请人： Chih-Hsien CHANG , Yung-Chow PENG , Fu-Lung HSUEH
发明人： Chih-Hsien CHANG , Yung-Chow PENG , Fu-Lung HSUEH
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/00 , G06F17/5009 , G06F17/5045 , G06F17/5068 , G06F19/00 , G06F2217/12 , G21K5/00
摘要： A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.
摘要翻译：电路设计系统包括被配置为产生电路的示意图信息和预着色信息的示意性设计工具。电路设计系统还包括被配置为在非暂时计算机可读介质上存储原理图信息和预着色信息的网表文件，以及被配置为从网表文件中提取预着色信息的提取工具。包括在电路设计系统中的布局设计工具被配置为基于原理图信息和预着色信息设计至少一个掩模。电路设计系统还包括布局与示意性比较工具，其被配置为将至少一个掩模与示意图信息和预着色信息进行比较。

4. 发明申请

US20130063181A1 METHOD AND APPARATUS FOR SIGNAL PHASE CALIBRATION 有权
标题翻译：信号相位校准的方法和装置
公开(公告)号：US20130063181A1
公开(公告)日：2013-03-14
申请号：US13228508
申请日：2011-09-09
申请人： Mao-Hsuan CHOU , Min-Shueh YUAN , Chih-Hsien CHANG
发明人： Mao-Hsuan CHOU , Min-Shueh YUAN , Chih-Hsien CHANG
IPC分类号： H03D13/00
CPC分类号： H03K5/135 , H03B19/00 , H03L7/099
摘要： A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.
摘要翻译：用于信号相位校准的方法包括提供多个周期性时钟信号，包括参考信号和参考信号的多个相移版本。这些信号具有共同的频率并且相互偏移倍数的相位偏移。检测到第一信号的边缘。第一个信号是参考信号的多个相移版本之一。边缘是从第一逻辑值到第二逻辑值的转换。第一信号的第二逻辑值在检测到边缘时被比较为除了第一信号之外的第一多个周期性时钟信号之一的第二信号的逻辑值。基于比较的结果选择性地提供第一信号的反转。

5. 发明申请

US20120124531A1 I/O CELL ARCHITECTURE 有权
标题翻译： I / O CELL ARCHITECTURE
公开(公告)号：US20120124531A1
公开(公告)日：2012-05-17
申请号：US12947938
申请日：2010-11-17
申请人： Renjeng CHIANG , Chih-Hsien CHANG
发明人： Renjeng CHIANG , Chih-Hsien CHANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/40
摘要： A system includes a computer readable storage medium and a processor. The computer readable storage includes data representing an input/output (“I/O”) cell of a first type for modeling and/or fabricating a semiconductor device. The I/O cell of the first type includes circuitry for providing a first plurality of functions. The processor is in communication with the computer readable storage medium and is configured to select the I/O cell of the first type, arrange a plurality of the I/O cells of the first type on a model of an semiconductor device, and store the model of the semiconductor device including the plurality of the I/O cells of the first type in the computer readable storage medium.
摘要翻译：系统包括计算机可读存储介质和处理器。计算机可读存储器包括表示用于建模和/或制造半导体器件的第一类型的输入/输出（“I / O”）单元的数据。第一类型的I / O单元包括用于提供第一多个功能的电路。处理器与计算机可读存储介质通信，并且被配置为选择第一类型的I / O单元，将第一类型的多个I / O单元布置在半导体器件的型号上，并存储包括计算机可读存储介质中第一类型的多个I / O单元的半导体器件的型号。

6. 发明申请

US20120285280A1 TRANSMISSION ASSEMBLY 审中-公开
标题翻译：传输总成
公开(公告)号：US20120285280A1
公开(公告)日：2012-11-15
申请号：US13345900
申请日：2012-01-09
申请人： Chih-Hsien CHANG
发明人： Chih-Hsien CHANG
IPC分类号： F16H35/10 , F16H1/14 , F16H1/12
CPC分类号： F16H35/10 , F16H1/14 , F16M11/045 , F16M11/046 , F16M11/18 , G02B7/022 , G02B7/023 , Y10T74/19633 , Y10T74/1966 , Y10T74/19665
摘要： A transmission assembly including a frame, driving and driven shafts, driving and driven gears and a knob is provided. The shafts are pivotally connected to the frame, and axes of the driving and driven shafts are intersected mutually. The driving gear is disposed at an end portion of the driving shaft, and the driven gear is disposed at an end portion of the driven shaft to engage with the driving gear. The knob is disposed at another end portion of the driving shaft for receiving torque to conduct the rotation of the driving and driven shafts and the driving and driven gears. When the torque is excessively large, the knob rotates against the driving gear, so the torque will not be transmitted to the gears. Moreover, when the gears are stuck, one of the driving and driven gears can move along the axis to increase backlash therebetween.
摘要翻译：提供了包括框架，驱动和从动轴，驱动和从动齿轮以及旋钮的传动组件。轴可枢转地连接到框架，并且驱动轴和从动轴的轴线相互相交。驱动齿轮配置在驱动轴的端部，从动齿轮配置在从动轴的端部，与驱动齿轮啮合。旋钮设置在驱动轴的另一端部，用于接收扭矩以传导驱动轴和从动轴以及驱动和从动齿轮的旋转。当转矩过大时，旋钮抵靠驱动齿轮旋转，因此转矩不会传递到齿轮。此外，当齿轮卡住时，驱动齿轮和从动齿轮中的一个可以沿着轴线移动以增加它们之间的间隙。

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