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    • 1. 发明授权
    • Non-destructive root cause analysis on blocked contact or via
    • 对破坏性接触或通过的非破坏性根本原因分析
    • US06777676B1
    • 2004-08-17
    • US10303267
    • 2002-11-21
    • Ying WangYeishin TungAnne Testoni
    • Ying WangYeishin TungAnne Testoni
    • G01N2300
    • G01N23/225H01J2237/2561
    • Disclosed are apparatus and methods for characterizing a potential defect of a semiconductor structure. A charged particle beam is scanned over a structure which has a potential defect. X-rays are detected from the scanned structure. The X-rays are in response to the charged particle beam being scanned over the structure. The potential defect of the scanned structure is characterized based on the detected X-rays. For example, it may be determined whether a potentially defective via has a SiO2 plug defect by comparing an X-ray count ratio of oxygen over silicon of the defective via with an X-ray count ratio of a known defect-free reference via. If the defective via has a relatively high ratio (more oxygen than silicon) as compared to the reference via, then it may be determined that a SiO2 plug defect is present within the defective via. Otherwise, the via may be defmed as having a different type of defect (e.g., not a SiO2 plug defect) or defined resulting in a “false” defect. Accordingly, specific embodiments of the present invention may be utilized to filter “false” defects from a defect sample.
    • 公开了用于表征半导体结构的潜在缺陷的装置和方法。 带电粒子束在具有潜在缺陷的结构上扫描。 从扫描结构检测X射线。 X射线响应于在结构上扫描的带电粒子束。 基于检测到的X射线来表征扫描结构的潜在缺陷。 例如,可以通过将有缺陷的通孔的硅上的氧的X射线计数比与已知的无缺陷参考通孔的X射线计数比进行比较,来确定潜在缺陷通孔是否具有SiO 2插塞缺陷。 如果故障通孔与参考通孔相比具有相对高的比率(比硅更多的氧),则可以确定在缺陷通孔内存在SiO 2插塞缺陷。 否则,可以将通孔定义为具有不同类型的缺陷(例如,不是SiO2插塞缺陷)或定义导致“假”缺陷。 因此,可以利用本发明的具体实施例来从缺陷样品中过滤“假”缺陷。
    • 2. 发明授权
    • Methods and apparatus for electron beam assisted etching at low temperatures
    • 低温电子束辅助蚀刻的方法和装置
    • US08202440B1
    • 2012-06-19
    • US11670928
    • 2007-02-02
    • Mehran Nasser-GhodsiYing WangHarrison ChinAnne TestoniR. Chris Burns
    • Mehran Nasser-GhodsiYing WangHarrison ChinAnne TestoniR. Chris Burns
    • C03C15/00C23F1/00
    • C23F4/00H01L21/32136
    • Disclosed are methods and apparatus for etching a sample, such as a semiconductor device or wafer. In general terms, embodiments of the present invention allow dry etching of a material on a sample, such as a copper material, at room temperature using a reactive substance, such as a chorine based gas. For example, the mechanisms of the present invention allow precise etching of a copper material to produce fine feature patterns without heating up the whole device or substrate to an elevated temperature such as 50° C. and above. The etching is assisted by simultaneously scanning a charged particle beam, such as an electron beam, and a photon beam, such as a laser beam, over a same target area of the sample while the reactive substance is introduced near the same target area. The reactive substance, charged particle beam, and photon beam act in combination to etch the sample at the target area. For example, a copper layer may be etched using the mechanisms of the present invention.
    • 公开了用于蚀刻诸如半导体器件或晶片的样品的方法和装置。 一般来说,本发明的实施方案允许使用反应性物质如基于氯化物的气体在室温下在样品(例如铜材料)上干燥蚀刻材料。 例如,本发明的机构允许铜材料的精确蚀刻以产生精细的特征图案,而不会将整个装置或基板加热到升高的温度,例如50℃及以上。 通过在样品的相同目标区域上同时扫描诸如电子束的带电粒子束和诸如激光束的光子束来辅助蚀刻,同时将反应物质引入到相同目标区域附近。 反应物质,带电粒子束和光子束组合起来,以在目标区域刻蚀样品。 例如,可以使用本发明的机构蚀刻铜层。
    • 3. 发明授权
    • Void characterization in metal interconnect structures using X-ray emission analyses
    • 使用X射线发射分析的金属互连结构中的空隙表征
    • US06924484B1
    • 2005-08-02
    • US10691940
    • 2003-10-22
    • Ying WangAnne Testoni
    • Ying WangAnne Testoni
    • G01N23/225G01Q30/02H01J37/256G01N23/223H01J37/153
    • H01J37/256G01N23/225H01J2237/2445H01J2237/2561H01J2237/2807
    • Disclosed are methods and apparatus for characterizing a potential void or voids by analyzing the X-ray count of one or more emitted X-ray species as emitted from an interconnect structure under test in response to a impinging beam, such as an electron beam, directed towards the sample surface. For example, this analysis may be used to determine whether the structure (e.g., a contact, line or via) has one or more void(s). It may also he used to help determine where the void(s) are with respect to the interconnect structure. It may also be used to help determine other characteristics of the void(s) with respect to the interconnect structure such as the shape(s) and size(s) of the void(s). The analysis may also be used to help initially determine whether the structure under test is so out of specification that it cannot then be determined whether the structure has a defect of a particular type. This analysis can be used to evaluate the process variation of wafers.
    • 公开了通过分析从被测互连结构发射的一个或多个发射的X射线物质的X射线计数来响应于诸如电子束的入射光束来指示潜在空隙或空隙的方法和装置,例如电子束 朝向样品表面。 例如,该分析可用于确定结构(例如,接触,线或通孔)是否具有一个或多个空隙。 他也可以帮助确定空隙相对于互连结构的位置。 它还可以用于帮助确定相对于互连结构的空隙的其它特征,例如空隙的形状和尺寸。 该分析还可以用于帮助最初确定被测结构是否超出规范,以致不能确定该结构是否具有特定类型的缺陷。 该分析可用于评估晶圆的工艺变化。
    • 4. 发明申请
    • In-situ process chamber preparation methods for plasma ion implantation systems
    • 等离子体离子注入系统的原位处理室制备方法
    • US20050260354A1
    • 2005-11-24
    • US10850222
    • 2004-05-20
    • Vikram SinghAtul GuptaHarold PersingSteven WaltherAnne Testoni
    • Vikram SinghAtul GuptaHarold PersingSteven WaltherAnne Testoni
    • H01J37/32C23C14/00C23C16/00
    • H01J37/32495H01J37/32412
    • A method for plasma ion implantation of a substrate includes providing a plasma ion implantation system including a process chamber, a source for producing a plasma in the process chamber, a platen for holding the substrate in the process chamber, and a voltage source for accelerating ions from the plasma into the substrate, depositing on interior surfaces of the process chamber a fresh coating that is similar in composition to a deposited film that results from plasma ion implantation of the substrate, before depositing the fresh coating, cleaning interior surfaces of the process chamber by removing an old film using one or more activated cleaning precursors, plasma ion implantation of the substrate according to a plasma ion implantation process, and repeating the steps of cleaning interior surfaces of the process chamber and depositing a fresh coating following plasma ion implantation of one or more substrates.
    • 用于等离子体离子注入衬底的方法包括提供等离子体离子注入系统,其包括处理室,用于在处理室中产生等离子体的源,用于将衬底保持在处理室中的压板和用于加速离子的电压源 从等离子体进入衬底,在沉积新鲜涂层之前,在沉积新鲜涂层之前,在处理室的内表面上沉积与组合物中与等离子体离子注入导致的沉积膜相似的新涂层,清洁处理室的内表面 通过使用一种或多种激活的清洁前体去除旧膜,根据等离子体离子注入工艺等离子体离子注入基板,并重复清洁处理室的内表面并在等离子体离子注入之后沉积新涂层的步骤 或更多的基材。