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1. 发明申请

US20120256267A1 Electrical Fuse Formed By Replacement Metal Gate Process 有权
标题翻译：通过更换金属浇口工艺形成的电保险丝
公开(公告)号：US20120256267A1
公开(公告)日：2012-10-11
申请号：US13080019
申请日：2011-04-05
申请人： Ying Li , Ramachandra Divakaruni
发明人： Ying Li , Ramachandra Divakaruni
IPC分类号： H01L27/06 , H01L21/768 , H01L21/28
CPC分类号： H01L23/5256 , H01L27/0629 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region.
摘要翻译：提供一种用于制造电熔丝和场效应晶体管的方法，所述场效应晶体管具有金属栅极，该金属栅极包括从覆盖衬底的电介质区域中的第一和第二开口去除材料，其中第一开口与衬底的有源半导体区域对准，并且所述第二开口与所述衬底的隔离区域对准，并且所述有源半导体区域包括与所述第一开口的边缘相邻的源极区域和漏极区域。可以形成电熔丝，其具有填充第二开口的熔丝元件，熔丝元件是单一导电材料的整体区域，金属或金属的导电化合物。可以形成在第一开口内延伸的金属栅极，以限定包括金属栅极和有源半导体区域的场效应晶体管（FET）。

2. 发明授权

US08536656B2 Self-aligned contacts for high k/metal gate process flow 有权
标题翻译：用于高k /金属栅极工艺流程的自对准触点
公开(公告)号：US08536656B2
公开(公告)日：2013-09-17
申请号：US12987221
申请日：2011-01-10
申请人： Ravikumar Ramachandran , Ramachandra Divakaruni , Ying Li
发明人： Ravikumar Ramachandran , Ramachandra Divakaruni , Ying Li
IPC分类号： H01L21/70
CPC分类号： H01L29/401 , H01L21/76895 , H01L21/76897 , H01L29/49 , H01L29/4983 , H01L29/51 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.
摘要翻译：提供一种半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层的半导体衬底。每个栅极堆叠包括从底部到顶部的高k栅极电介质层，功函数金属层和导电金属。间隔件位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫存在于每个间隔件的上表面上。每个自对准电介质衬垫的底表面存在于半导体金属合金的上表面上。接触金属位于相邻的栅极堆叠之间，并通过自对准电介质衬垫与每个栅极堆叠分离。该结构还包括另一个接触金属，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及位于与其中一个栅极叠层的导电金属直接接触的另一部分。还公开了使用替换栅极和非替代栅极方案形成半导体结构的方法。

3. 发明授权

US08367494B2 Electrical fuse formed by replacement metal gate process 有权
标题翻译：电气保险丝由更换金属栅工艺形成
公开(公告)号：US08367494B2
公开(公告)日：2013-02-05
申请号：US13080019
申请日：2011-04-05
申请人： Ying Li , Ramachandra Divakaruni
发明人： Ying Li , Ramachandra Divakaruni
IPC分类号： H01L21/8238
CPC分类号： H01L23/5256 , H01L27/0629 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region.
摘要翻译：提供一种用于制造电熔丝和场效应晶体管的方法，所述场效应晶体管具有金属栅极，该金属栅极包括从覆盖衬底的电介质区域中的第一和第二开口去除材料，其中所述第一开口与所述衬底的有源半导体区域对准，并且所述第二开口与所述衬底的隔离区域对准，并且所述有源半导体区域包括与所述第一开口的边缘相邻的源极区域和漏极区域。可以形成电熔丝，其具有填充第二开口的熔丝元件，熔丝元件是单一导电材料的整体区域，金属或金属的导电化合物。可以形成在第一开口内延伸的金属栅极，以限定包括金属栅极和有源半导体区域的场效应晶体管（FET）。

4. 发明申请

US20120175711A1 Self-Aligned Contacts for High k/Metal Gate Process Flow 有权
标题翻译：用于高k /金属栅极工艺流程的自对准触点
公开(公告)号：US20120175711A1
公开(公告)日：2012-07-12
申请号：US12987221
申请日：2011-01-10
申请人： Ravikumar Ramachandran , Ramachandra Divakaruni , Ying Li
发明人： Ravikumar Ramachandran , Ramachandra Divakaruni , Ying Li
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/401 , H01L21/76895 , H01L21/76897 , H01L29/49 , H01L29/4983 , H01L29/51 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.
摘要翻译：提供一种半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层的半导体衬底。每个栅极堆叠包括从底部到顶部的高k栅极电介质层，功函数金属层和导电金属。间隔件位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫存在于每个间隔件的上表面上。每个自对准电介质衬垫的底表面存在于半导体金属合金的上表面上。接触金属位于相邻的栅极堆叠之间，并通过自对准电介质衬垫与每个栅极堆叠分离。该结构还包括另一个接触金属，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及位于与其中一个栅极叠层的导电金属直接接触的另一部分。还公开了使用替换栅极和非替代栅极方案形成半导体结构的方法。

5. 发明授权

US09515140B2 Patterned strained semiconductor substrate and device 有权
标题翻译：图形应变半导体衬底和器件
公开(公告)号：US09515140B2
公开(公告)日：2016-12-06
申请号：US12015272
申请日：2008-01-16
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L29/73 , H01L29/10 , H01L29/739 , H01L29/786 , H01L21/8234
CPC分类号： H01L29/1054 , H01L21/823412 , H01L29/739 , H01L29/78687
摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.
摘要翻译：一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。该结构包括具有图案化的应变和非应变材料的多层基底。

6. 发明授权

US08703552B2 Method and structure for forming capacitors and memory devices on semiconductor-on-insulator (SOI) substrates 有权
标题翻译：用于在半导体绝缘体（SOI）衬底上形成电容器和存储器件的方法和结构
公开(公告)号：US08703552B2
公开(公告)日：2014-04-22
申请号：US13419624
申请日：2012-03-14
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L27/06 , H01L21/8242
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1087 , H01L27/10894 , H01L27/1203 , H01L29/66181
摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
摘要翻译：提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。还提供了一种用于形成上述装置的方法。

7. 发明授权

US08492818B2 High capacitance trench capacitor 有权
标题翻译：高电容沟槽电容
公开(公告)号：US08492818B2
公开(公告)日：2013-07-23
申请号：US12881481
申请日：2010-09-14
申请人： Keith Kwong Hon Wong , Ramachandra Divakaruni , Roger A. Booth, Jr.
发明人： Keith Kwong Hon Wong , Ramachandra Divakaruni , Roger A. Booth, Jr.
IPC分类号： H01L27/108
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.
摘要翻译：双节点介质沟槽电容器包括在沟槽中形成的一叠层。层的堆叠包括从底部到顶部的第一导电层，第一节点电介质层，第二导电层，第二节点电介质层和第三导电层。双节点介电沟槽电容器包括两个背对背电容器，其包括第一电容器和第二电容器。第一电容器包括第一导电层，第一节点电介质层，第二导电层，第二电容器包括第二导电层，第二节点电介质层和第三导电层。双节点介质沟槽电容器可以提供使用具有与第一和第二节点电介质层相当的组成和厚度的单节点电介质层的沟槽电容器的大约两倍的电容。

8. 发明授权

US08236634B1 Integration of fin-based devices and ETSOI devices 有权
标题翻译：集成了鳍式设备和ETSOI设备
公开(公告)号：US08236634B1
公开(公告)日：2012-08-07
申请号：US13050023
申请日：2011-03-17
申请人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Narasimhulu Kanike , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L27/088
CPC分类号： H01L27/1211 , H01L21/845
摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.
摘要翻译：薄半导体区域和厚半导体区域被形成为绝缘体层。厚半导体区域包括至少一个半导体鳍片。图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。此外，翅片源极和漏极区域在薄的鳍部上生长。源极和漏极区域，鳍片和一次性栅电极被平坦化。一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

9. 发明申请

US20120171821A1 METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES 有权
标题翻译：在半导体绝缘体（SOI）衬底上形成电容器和存储器件的方法和结构
公开(公告)号：US20120171821A1
公开(公告)日：2012-07-05
申请号：US13419624
申请日：2012-03-14
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L21/786
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1087 , H01L27/10894 , H01L27/1203 , H01L29/66181
摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
摘要翻译：提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。还提供了一种用于形成上述装置的方法。

10. 发明授权

US07919347B2 Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes 有权
标题翻译：制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构
公开(公告)号：US07919347B2
公开(公告)日：2011-04-05
申请号：US12349018
申请日：2009-01-06
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
IPC分类号： H01L29/868
CPC分类号： H01L29/868 , H01L29/6609
摘要： Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
摘要翻译：制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构。一种方法包括：在硅衬底中形成沟槽; 在所述衬底中形成邻接所述沟槽的掺杂区域; 在沟槽的表面上生长本征的外延硅层; 沉积掺杂多晶硅层以填充沟槽中的剩余空间，执行化学机械抛光，使得本征外延硅层和掺杂多晶硅层的顶表面是共面的; 在衬底中形成绝缘隔离层; 在隔离层的顶部形成介电层; 以及通过介电层形成第一金属接触到掺杂多晶硅层，以及通过第二接触到掺杂区域介电层并通过隔离层。

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