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1. 发明申请

US20110127541A1 SEMICONDUCTOR HETEROSTRUCTURE DIODES 有权
标题翻译：半导体结构二极管
公开(公告)号：US20110127541A1
公开(公告)日：2011-06-02
申请号：US13008874
申请日：2011-01-18
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
IPC分类号： H01L29/02
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

2. 发明申请

US20100140660A1 Semiconductor Heterostructure Diodes 有权
标题翻译：半导体异质结二极管
公开(公告)号：US20100140660A1
公开(公告)日：2010-06-10
申请号：US12332284
申请日：2008-12-10
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
IPC分类号： H01L29/872
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

3. 发明授权

US08541818B2 Semiconductor heterostructure diodes 有权
标题翻译：半导体异质结二极管
公开(公告)号：US08541818B2
公开(公告)日：2013-09-24
申请号：US13533339
申请日：2012-06-26
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Ilan Ben-Yaacov
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Ilan Ben-Yaacov
IPC分类号： H01L33/00 , H01L29/739
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2 DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2 DEG, forming an ohmic contact with the layer containing the 2 DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2°的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触器连接到2°，与含有2°的层形成欧姆接触。

4. 发明授权

US08237198B2 Semiconductor heterostructure diodes 有权
标题翻译：半导体异质结二极管
公开(公告)号：US08237198B2
公开(公告)日：2012-08-07
申请号：US13008874
申请日：2011-01-18
申请人： Yifeng Wu , Rongming Chu , Primit Parikh , Umesh Mishra , Ilan Ben-Yaacov , Likun Shen
发明人： Yifeng Wu , Rongming Chu , Primit Parikh , Umesh Mishra , Ilan Ben-Yaacov , Likun Shen
IPC分类号： H01L33/00 , H01L29/739
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

5. 发明申请

US20120267640A1 SEMICONDUCTOR HETEROSTRUCTURE DIODES 有权
标题翻译：半导体结构二极管
公开(公告)号：US20120267640A1
公开(公告)日：2012-10-25
申请号：US13533339
申请日：2012-06-26
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Ilan Ben-Yaacov
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Ilan Ben-Yaacov
IPC分类号： H01L29/20
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

6. 发明授权

US07898004B2 Semiconductor heterostructure diodes 有权
标题翻译：半导体异质结二极管
公开(公告)号：US07898004B2
公开(公告)日：2011-03-01
申请号：US12332284
申请日：2008-12-10
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
IPC分类号： H01L29/739 , H01L33/00
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

7. 发明授权

US08519438B2 Enhancement mode III-N HEMTs 有权
公开(公告)号：US08519438B2
公开(公告)日：2013-08-27
申请号：US12108449
申请日：2008-04-23
申请人： Umesh Mishra , Robert Coffie , Likun Shen , Ilan Ben-Yaacov , Primit Parikh
发明人： Umesh Mishra , Robert Coffie , Likun Shen , Ilan Ben-Yaacov , Primit Parikh
IPC分类号： H01L29/66
CPC分类号： H01L29/7784 , H01L21/0217 , H01L21/0254 , H01L29/0847 , H01L29/1033 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/365 , H01L29/4236 , H01L29/518 , H01L29/66431 , H01L29/66462 , H01L29/7783 , H01L29/7787 , H01L29/7788
摘要： A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

8. 发明申请

US20090267078A1 Enhancement Mode III-N HEMTs 有权
标题翻译：增强模式III-N HEMTs
公开(公告)号：US20090267078A1
公开(公告)日：2009-10-29
申请号：US12108449
申请日：2008-04-23
申请人： Umesh Mishra , Robert Coffie , Likun Shen , Ilan Ben-Yaacov , Primit Parikh
发明人： Umesh Mishra , Robert Coffie , Likun Shen , Ilan Ben-Yaacov , Primit Parikh
IPC分类号： H01L29/778 , H01L21/338
CPC分类号： H01L29/7784 , H01L21/0217 , H01L21/0254 , H01L29/0847 , H01L29/1033 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/365 , H01L29/4236 , H01L29/518 , H01L29/66431 , H01L29/66462 , H01L29/7783 , H01L29/7787 , H01L29/7788
摘要： A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.
摘要翻译：一种III-N半导体器件，其包括衬底和包括部分在栅极区域下方的区域的氮化物沟道层，以及在栅极下方的部分的相对侧上的两个沟道存取区域。通道接入区域可以在与栅极下方的区域不同的层中。该器件包括与沟道层相邻的AlXN层，其中X是镓，铟或它们的组合，以及在与沟道接入区相邻的区域中与AlXN层相邻的优选n掺杂GaN层。选择AlXN层中的Al的浓度，n掺杂GaN层中的AlXN层厚度和n掺杂浓度，以在沟道接入区域中引起2DEG电荷，而不在栅极下方引起任何实质的2DEG电荷，使得在没有施加到栅极的开关电压的情况下，通道不导通。

9. 发明申请

US20110193619A1 SEMICONDUCTOR ELECTRONIC COMPONENTS AND CIRCUITS 有权
标题翻译：半导体电子元件和电路
公开(公告)号：US20110193619A1
公开(公告)日：2011-08-11
申请号：US12701458
申请日：2010-02-05
申请人： Primit Parikh , James Honea , Carl C. Blake, JR. , Robert Coffie , Yifeng Wu , Umesh Mishra
发明人： Primit Parikh , James Honea , Carl C. Blake, JR. , Robert Coffie , Yifeng Wu , Umesh Mishra
IPC分类号： H03K3/01 , H01L27/06
CPC分类号： H01L27/0883 , H01L21/8258 , H01L23/49562 , H01L23/49575 , H01L23/642 , H01L23/647 , H01L25/165 , H01L25/18 , H01L27/0605 , H01L2224/48137 , H01L2224/48195 , H01L2224/48247 , H01L2224/48257 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/30107 , H03K17/567 , H01L2924/00
摘要： An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.
摘要翻译：电子部件包括高压耗尽型晶体管和低压增强型晶体管，两者都封装在单个封装中。高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的漏极电连接到漏极引线单个封装，低电压增强型晶体管的栅电极电连接到单个封装的栅极引线，高电压耗尽型晶体管的栅极电连接到单个封装的附加引线并且低电压增强型晶体管的源电极电连接到单个封装的导电结构部分。

10. 发明申请

US20110114997A1 HIGH VOLTAGE GaN TRANSISTORS 有权
标题翻译：高电压GaN晶体管
公开(公告)号：US20110114997A1
公开(公告)日：2011-05-19
申请号：US13014619
申请日：2011-01-26
申请人： YIFENG WU , Primit Parikh , Umesh Mishra
发明人： YIFENG WU , Primit Parikh , Umesh Mishra
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404 , H01L29/66462 , H01L29/7786
摘要： A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.
摘要翻译：多场板晶体管包括有源区，源极，漏极和栅极。第一间隔层在源极和栅极之间的有源区上方，并且在漏极和栅极之间的有源区上方具有第二间隔层。第一间隔层上的第一场板连接到栅极。第二间隔层上的第二场板连接到栅极。第三间隔层位于第一间隔层，第二间隔层，第一场板，栅极和第二场板上，在第三间隔层上具有第三场板并连接到源极。晶体管表现出至少600伏特的阻断电压，同时支持至少2安培的电流，其导通电阻不超过5.0mΩ（OHgr·-cm2）为至少600伏，同时支持至少3安培的电流耐电压不超过5.3mΩ，OHgr--cm2，至少900V，同时支持至少2安培的电流，导通电阻不超过6.6mΩ，OHgr-cm2，或阻断电压至少为900V，同时支持至少3安培的电流，导通电阻不超过7.0mΩ，OHgr; -cm2。

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