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1. 发明申请

US20110114997A1 HIGH VOLTAGE GaN TRANSISTORS 有权
标题翻译：高电压GaN晶体管
公开(公告)号：US20110114997A1
公开(公告)日：2011-05-19
申请号：US13014619
申请日：2011-01-26
申请人： YIFENG WU , Primit Parikh , Umesh Mishra
发明人： YIFENG WU , Primit Parikh , Umesh Mishra
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404 , H01L29/66462 , H01L29/7786
摘要： A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.
摘要翻译：多场板晶体管包括有源区，源极，漏极和栅极。第一间隔层在源极和栅极之间的有源区上方，并且在漏极和栅极之间的有源区上方具有第二间隔层。第一间隔层上的第一场板连接到栅极。第二间隔层上的第二场板连接到栅极。第三间隔层位于第一间隔层，第二间隔层，第一场板，栅极和第二场板上，在第三间隔层上具有第三场板并连接到源极。晶体管表现出至少600伏特的阻断电压，同时支持至少2安培的电流，其导通电阻不超过5.0mΩ（OHgr·-cm2）为至少600伏，同时支持至少3安培的电流耐电压不超过5.3mΩ，OHgr--cm2，至少900V，同时支持至少2安培的电流，导通电阻不超过6.6mΩ，OHgr-cm2，或阻断电压至少为900V，同时支持至少3安培的电流，导通电阻不超过7.0mΩ，OHgr; -cm2。

2. 发明申请

US20100109051A1 HIGH VOLTAGE GAN TRANSISTORS 有权
标题翻译：高电压晶体管
公开(公告)号：US20100109051A1
公开(公告)日：2010-05-06
申请号：US12636019
申请日：2009-12-11
申请人： YIFENG WU , Primit Parikh , Umesh Mishra
发明人： YIFENG WU , Primit Parikh , Umesh Mishra
IPC分类号： H01L29/778 , H01L29/80
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404 , H01L29/66462 , H01L29/7786
摘要： A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.
摘要翻译：多场板晶体管包括有源区，源极，漏极和栅极。第一间隔层在源极和栅极之间的有源区上方，并且在漏极和栅极之间的有源区上方具有第二间隔层。第一间隔层上的第一场板连接到栅极。第二间隔层上的第二场板连接到栅极。第三间隔层位于第一间隔层，第二间隔层，第一场板，栅极和第二场板上，在第三间隔层上具有第三场板并连接到源极。晶体管表现出至少600伏特的阻断电压，同时支持至少2安培的电流，其导通电阻不超过5.0mΩ（OHgr·-cm2）为至少600伏，同时支持至少3安培的电流耐电压不超过5.3mΩ，OHgr--cm2，至少900V，同时支持至少2安培的电流，导通电阻不超过6.6mΩ，OHgr-cm2，或阻断电压至少为900V，同时支持至少3安培的电流，导通电阻不超过7.0mΩ，OHgr; -cm2。

3. 发明申请

US20120132959A1 WIDE BANDGAP TRANSISTOR DEVICES WITH FIELD PLATES 有权
标题翻译：具有现场板的宽带状晶体管器件
公开(公告)号：US20120132959A1
公开(公告)日：2012-05-31
申请号：US13355766
申请日：2012-01-23
申请人： PRIMIT PARIKH , YIFENG WU
发明人： PRIMIT PARIKH , YIFENG WU
IPC分类号： H01L29/778
CPC分类号： H01L29/402 , H01L29/1608 , H01L29/2003 , H01L29/42316 , H01L29/7787 , H01L29/812
摘要： A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact and provides a reduction in the peak operational electric field.
摘要翻译：一种晶体管结构，包括具有金属源的有源半导体层和与该有源层电接触形成的漏极触点。在源极和漏极接触之间形成栅极接触，用于调制有源层内的电场。在有源层上方形成间隔层，形成在间隔层上方的导电场板，从栅极接触边缘向漏极接触延伸一段距离Lf。场板电连接到栅极接触并且提供峰值操作电场的减小。

4. 发明申请

US20110220966A1 ROBUST TRANSISTORS WITH FLUORINE TREATMENT 有权
标题翻译：具有荧光处理的稳定晶体管
公开(公告)号：US20110220966A1
公开(公告)日：2011-09-15
申请号：US13112285
申请日：2011-05-20
申请人： YIFENG WU , Marcia Moore , Tim Wisleder , Primit Parikh
发明人： YIFENG WU , Marcia Moore , Tim Wisleder , Primit Parikh
IPC分类号： H01L29/778
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/66462
摘要： A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.
摘要翻译：具有多个外延层并经历操作（E）场的半导体器件，特别是高电子迁移率晶体管（HEMT）。在外延层中的负离子区域以对抗操作（E）场。制造半导体器件的一种方法包括在衬底上提供衬底和生长外延层。将负离子引入外延层中以形成负离子区域以对抗半导体器件中的电（E）场。可以在形成负离子区之前或之后将触点沉积在外延层上。

5. 发明申请

US20100041188A1 ROBUST TRANSISTORS WITH FLUORINE TREATMENT 有权
标题翻译：具有荧光处理的稳定晶体管
公开(公告)号：US20100041188A1
公开(公告)日：2010-02-18
申请号：US12581977
申请日：2009-10-20
申请人： YIFENG WU , MARCIA MOORE , TIM WISLEDER , PRIMIT PARIKH
发明人： YIFENG WU , MARCIA MOORE , TIM WISLEDER , PRIMIT PARIKH
IPC分类号： H01L21/335 , H01L21/20
CPC分类号： H01L29/7783 , H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/66462
摘要： A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.
摘要翻译：具有多个外延层并经历操作（E）场的半导体器件，特别是高电子迁移率晶体管（HEMT）。在外延层中的负离子区域以对抗操作（E）场。制造半导体器件的一种方法包括在衬底上提供衬底和生长外延层。将负离子引入外延层中以形成负离子区域以对抗半导体器件中的电（E）场。可以在形成负离子区之前或之后将触点沉积在外延层上。

6. 发明申请

US20120049243A1 GAN BASED HEMTS WITH BURIED FIELD PLATES 审中-公开
标题翻译：基于GAN的HEMTS与BURIED现场板
公开(公告)号：US20120049243A1
公开(公告)日：2012-03-01
申请号：US13245579
申请日：2011-09-26
申请人： YIFENG WU
发明人： YIFENG WU
IPC分类号： H01L29/778
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786 , H01L29/7787 , H01L29/8128
摘要： A transistor with source and drain electrodes formed in contact with an active region and a gate between the source and drain electrodes and in contact with the active region. A first spacer layer is on at least part of the active region surface between the gate and drain electrodes and between the gate and source electrodes. The gate comprises a generally t-shaped top portion that extends toward the source and drain electrodes. A field plate is on the spacer layer and under the overhang of at least one section of the gate top portion. The field plate is at least partially covered by a second spacer layer that is on at least part of the first active layer surface and between the gate and drain and between the gate and source. At least one conductive path electrically connects the field plate to the source electrode or the gate.
摘要翻译：一种晶体管，其源极和漏极形成为与有源区接触，并且源极和漏极之间的栅极与有源区接触。第一间隔层位于栅极和漏极之间以及栅极和源极之间的有源区表面的至少一部分上。栅极包括朝向源极和漏极延伸的大致t形的顶部部分。场板位于间隔层上并且在栅极顶部的至少一个部分的突出部之下。场板至少部分被第二间隔层覆盖，第二间隔层位于第一有源层表面的至少一部分上，栅极和漏极之间以及栅极和源极之间。至少一个导电路径将场板电连接到源电极或栅极。

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