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1. 发明授权

US08163607B2 Semiconductor device and method of making the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08163607B2
公开(公告)日：2012-04-24
申请号：US12769649
申请日：2010-04-29
申请人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
发明人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
IPC分类号： H01L21/8283
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/26513 , H01L21/2652 , H01L21/28518 , H01L21/823443 , H01L21/823835 , H01L29/6659 , H01L29/7833
摘要： In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
摘要翻译：在本发明的方法中，在自对准硅化物工艺中，在第二热处理之前，将掺杂剂注入位于从中间高度的NixSi层到其前面的区域中，或者在形成NixSi层之前位于从NiSi层的预定厚度的一半的深度到位于NiSi层的预定前方的深度的硅层的范围内。在第二热处理期间允许掺杂剂与NixSi层一起加热以形成Si / NiSi 2 / NiSi界面，其可以降低SBH并提高串联电阻以获得具有优异性能的半导体器件。

2. 发明授权

US08067281B1 Method of fabricating complementary metal-oxide-semiconductor (CMOS) Device 有权
标题翻译：互补金属氧化物半导体（CMOS）器件的制造方法
公开(公告)号：US08067281B1
公开(公告)日：2011-11-29
申请号：US12830371
申请日：2010-07-05
申请人： Yi-Wei Chen , Chien-Chung Huang , Nien-Ting Ho , Kuo-Chih Lai
发明人： Yi-Wei Chen , Chien-Chung Huang , Nien-Ting Ho , Kuo-Chih Lai
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7848
摘要： A method of fabricating a CMOS device is provided. First, first and second gates, first and second offset spacers and first and second lightly-doped regions are respectively formed in first and second type metal-oxide-semiconductor regions. A mask layer is respectively formed on the first and second gates. Next, an epitaxial layer is formed in the substrate on two sides of the second gate. Next, first and second spacers, first and second doped regions are formed. Next, a portion of the first spacer is removed to expose a portion of a surface of the first lightly-doped region, thereby forming a first slimmed spacer. Next, a coating layer containing silicon is formed to cover the exposed first lightly-doped region, the first and second doped regions. Next, the mask layer is removed. Next, a metal silicide layer is formed on the first and second gates and the silicon layer.
摘要翻译：提供一种制造CMOS器件的方法。首先，第一和第二栅极分别在第一和第二类型金属氧化物半导体区域中形成第一和第二偏移间隔物以及第一和第二轻掺杂区域。掩模层分别形成在第一和第二栅极上。接下来，在第二栅极的两侧的基板中形成外延层。接下来，形成第一和第二间隔物，形成第一和第二掺杂区域。接下来，去除第一间隔物的一部分以暴露第一轻掺杂区域的表面的一部分，从而形成第一细长间隔物。接下来，形成包含硅的涂层以覆盖暴露的第一轻掺杂区域，第一和第二掺杂区域。接下来，去除掩模层。接下来，在第一和第二栅极和硅层上形成金属硅化物层。

3. 发明申请

US20120181635A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20120181635A1
公开(公告)日：2012-07-19
申请号：US13424398
申请日：2012-03-20
申请人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
发明人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/26513 , H01L21/2652 , H01L21/28518 , H01L21/823443 , H01L21/823835 , H01L29/6659 , H01L29/7833
摘要： In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
摘要翻译：在本发明的方法中，在自对准硅化物工艺中，在第二热处理之前，将掺杂剂注入位于从中间高度的NixSi层到其前面的区域中，或者在形成NixSi层之前位于从NiSi层的预定厚度的一半的深度到位于NiSi层的预定前方的深度的硅层的范围内。在第二热处理期间允许掺杂剂与NixSi层一起加热以形成Si / NiSi 2 / NiSi界面，其可以降低SBH并提高串联电阻以获得具有优异性能的半导体器件。

4. 发明申请

US20110266596A1 Semiconductor device and method of making the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110266596A1
公开(公告)日：2011-11-03
申请号：US12769649
申请日：2010-04-29
申请人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
发明人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/26513 , H01L21/2652 , H01L21/28518 , H01L21/823443 , H01L21/823835 , H01L29/6659 , H01L29/7833
摘要： In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
摘要翻译：在本发明的方法中，在自对准硅化物工艺中，在第二热处理之前，将掺杂剂注入位于从中间高度的NixSi层到其前面的区域中，或者在形成NixSi层之前位于从NiSi层的预定厚度的一半的深度到位于NiSi层的预定前方的深度的硅层的范围内。在第二热处理期间允许掺杂剂与NixSi层一起加热以形成Si / NiSi 2 / NiSi界面，其可以降低SBH并提高串联电阻以获得具有优异性能的半导体器件。

5. 发明授权

US08344465B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08344465B2
公开(公告)日：2013-01-01
申请号：US13424398
申请日：2012-03-20
申请人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
发明人： Yi-Wei Chen , Nien-Ting Ho , Kuo-Chih Lai , Chien-Chung Huang
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/26513 , H01L21/2652 , H01L21/28518 , H01L21/823443 , H01L21/823835 , H01L29/6659 , H01L29/7833
摘要： In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at middle height down to a front thereof, or before formation of the NixSi layer, located in a region ranging from a silicon layer at a depth ranging from a half of a predetermined thickness of a NiSi layer down to a depth where is a predetermined front of the NiSi layer. The dopant is allowed to be heated with the NixSi layer together during the second thermal process to form a Si/NiSi2/NiSi interface which may reduce SBH and improve series resistance to obtain a semiconductor device having an excellent performance.
摘要翻译：在本发明的方法中，在自对准硅化物工艺中，在第二热处理之前，将掺杂剂注入位于从中间高度的NixSi层到其前面的区域中，或者在形成NixSi层之前位于从NiSi层的预定厚度的一半的深度到位于NiSi层的预定前方的深度的硅层的范围内。在第二热处理期间允许掺杂剂与NixSi层一起加热以形成Si / NiSi 2 / NiSi界面，其可以降低SBH并提高串联电阻以获得具有优异性能的半导体器件。

6. 发明申请

US20120088345A1 METHOD OF FORMING SILICIDE FOR CONTACT PLUGS 审中-公开
标题翻译：形成接触片硅氧烷的方法
公开(公告)号：US20120088345A1
公开(公告)日：2012-04-12
申请号：US12902149
申请日：2010-10-12
申请人： Yi-Wei Chen , Kuo-Chih Lai , Nien-Ting Ho , Chien-Chung Huang
发明人： Yi-Wei Chen , Kuo-Chih Lai , Nien-Ting Ho , Chien-Chung Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/28518 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A method for forming silicide is provided. First, a substrate is provided. Second, a gate structure is formed on the substrate which includes a silicon layer, a gate dielectric layer and at least one spacer. Then, a pair of source and drain is formed in the substrate and adjacent to the gate structure. Later, an interlayer dielectric layer is formed to cover the gate structure, the source and the drain. Afterwards, the interlayer dielectric layer is selectively removed to expose the gate structure. Next, multiple contact holes are formed in the interlayer dielectric layer to expose part of the substrate. Afterwards, the exposed substrate is converted to form silicide.
摘要翻译：提供了一种形成硅化物的方法。首先，提供基板。其次，在包括硅层，栅极电介质层和至少一个间隔物的基板上形成栅极结构。然后，在衬底中形成一对源极和漏极，并且与栅极结构相邻。然后，形成层间电介质层以覆盖栅极结构，源极和漏极。然后，选择性地去除层间绝缘层以露出栅极结构。接下来，在层间电介质层中形成多个接触孔，露出基板的一部分。之后，将曝光的基底转变成硅化物。

7. 发明授权

US09048254B2 Semiconductor structure having a metal gate with side wall spacers 有权
标题翻译：具有带有侧壁间隔物的金属栅极的半导体结构
公开(公告)号：US09048254B2
公开(公告)日：2015-06-02
申请号：US12629064
申请日：2009-12-02
申请人： Yi-Wei Chen , Nien-Ting Ho , Chien-Chung Huang , Chin-Fu Lin
发明人： Yi-Wei Chen , Nien-Ting Ho , Chien-Chung Huang , Chin-Fu Lin
IPC分类号： H01L29/66 , H01L21/28 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/2633 , H01L21/28026 , H01L21/28114 , H01L29/401 , H01L29/42372 , H01L29/42376 , H01L29/495 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66583 , H01L29/7833
摘要： A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.
摘要翻译：一种形成具有金属栅极的半导体结构的方法。首先，提供半导体衬底。随后，至少在半导体衬底上形成栅极结构。之后，形成围绕栅结构的间隔结构。然后，形成层间电介质。之后，对层间电介质进行平面化处理。然后，去除牺牲层的一部分以形成初始蚀刻深度，使得形成开口以露出间隔物结构的一部分。暴露于开口的间隔结构的部分被去除以扩大开口。之后，通过开口完全除去牺牲层。最后，形成栅极导电层以填充开口。

8. 发明申请

US20110127589A1 SEMICONDUCTOR STRUCTURE HAIVNG A METAL GATE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体结构具有金属门及其形成方法
公开(公告)号：US20110127589A1
公开(公告)日：2011-06-02
申请号：US12629064
申请日：2009-12-02
申请人： Yi-Wei Chen , Nien-Ting Ho , Chien-Chung Huang , Chin-Fu Lin
发明人： Yi-Wei Chen , Nien-Ting Ho , Chien-Chung Huang , Chin-Fu Lin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/2633 , H01L21/28026 , H01L21/28114 , H01L29/401 , H01L29/42372 , H01L29/42376 , H01L29/495 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66583 , H01L29/7833
摘要： A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.
摘要翻译：一种形成具有金属栅极的半导体结构的方法。首先，提供半导体衬底。随后，至少在半导体衬底上形成栅极结构。之后，形成围绕栅结构的间隔结构。然后，形成层间电介质。之后，对层间电介质进行平面化处理。然后，去除牺牲层的一部分以形成初始蚀刻深度，使得形成开口以露出间隔物结构的一部分。暴露于开口的间隔结构的部分被去除以扩大开口。之后，通过开口完全除去牺牲层。最后，形成栅极导电层以填充开口。

9. 发明授权

US08507350B2 Fabricating method of semiconductor elements 有权
标题翻译：半导体元件的制造方法
公开(公告)号：US08507350B2
公开(公告)日：2013-08-13
申请号：US13238045
申请日：2011-09-21
申请人： Chien-Chung Huang , Nien-Ting Ho
发明人： Chien-Chung Huang , Nien-Ting Ho
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L21/76814 , H01L21/823425 , H01L29/66628 , H01L29/66636
摘要： A fabricating method of a semiconductor element includes the following steps. First, a substrate is provided. A metal gate structure and source/drain electrodes are already formed on the substrate. An amorphization process is performed in the source/drain electrodes to form an amorphous portion. An interlayer dielectric layer is formed on surfaces of the source/drain electrodes and a through hole contact is formed within the interlayer dielectric layer. A silicidation process is performed with the through hole contact and the amorphous portion of the source/drain electrodes to form a metal silicide layer. The fabricating method is capable of finishing the formation of the metal silicide layer in the condition that diameters of the through hole contact is becoming smaller and smaller.
摘要翻译：半导体元件的制造方法包括以下步骤。首先，提供基板。金属栅极结构和源极/漏极已经形成在衬底上。在源/漏电极中进行非晶化处理以形成非晶部分。在源/漏电极的表面上形成层间电介质层，并且在层间电介质层内形成通孔接触。利用通孔接触和源极/漏极的非晶部分进行硅化处理以形成金属硅化物层。该制造方法能够在通孔接触的直径变得越来越小的条件下完成金属硅化物层的形成。

10. 发明申请

US20130149820A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20130149820A1
公开(公告)日：2013-06-13
申请号：US13323763
申请日：2011-12-12
申请人： Chien-Chung Huang , Kuo-Chih Lai
发明人： Chien-Chung Huang , Kuo-Chih Lai
IPC分类号： H01L21/8238
CPC分类号： H01L29/6659 , H01L21/28518 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7833 , H01L29/7847 , H01L29/7848
摘要： A method for manufacturing a semiconductor device includes providing a substrate having a first transistor device and a second transistor device formed thereon; forming a patterned stress film covering the second transistor device and exposing the first transistor device on the substrate; performing a pre-amorphous implantation (PAI) process to form an amorphous layer respectively at two sides of the first transistor device, and removing the patterned stress film.
摘要翻译：一种半导体器件的制造方法，包括提供具有第一晶体管器件和形成在其上的第二晶体管器件的衬底; 形成覆盖所述第二晶体管器件并使所述第一晶体管器件暴露于所述衬底上的图案化应力膜; 执行预非晶注入（PAI）工艺以分别在第一晶体管器件的两侧形成非晶层，以及去除图案化的应力膜。

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