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1. 发明申请

US20100231497A1 DISPLAY DEVICE PROVIDING BI-DIRECTIONAL VOLTAGE STABILIZATION 有权
标题翻译：显示器件提供双向电压稳定
公开(公告)号：US20100231497A1
公开(公告)日：2010-09-16
申请号：US12560443
申请日：2009-09-16
申请人： Yi-Suei Liao , Chien-Liang Chen , Ming-Yen Tsai
发明人： Yi-Suei Liao , Chien-Liang Chen , Ming-Yen Tsai
IPC分类号： G09G3/36
CPC分类号： G09G3/3677
摘要： An LCD device includes a plurality of gate lines and a plurality of shift register units for driving corresponding gate lines. Each shift register unit includes a first circuit and a second circuit. The first circuit, disposed on a first side of a corresponding gate line, includes a pulse generator and a first transistor having a first W/L ratio. The pulse generator provides a driving signal according to the voltage obtained at a node, while the first transistor maintains the voltage level of the node. The second circuit, disposed on a second side of the corresponding gate line, includes a second transistor having a second W/L ratio. The second transistor maintains the voltage level of the driving signal from the second side of the corresponding gate line. The first W/L ratio is smaller than the second W/L ratio, and the first circuit occupies larger space than the second circuit.
摘要翻译： LCD装置包括多个栅极线和用于驱动相应的栅极线的多个移位寄存器单元。每个移位寄存器单元包括第一电路和第二电路。布置在对应的栅极线的第一侧上的第一电路包括脉冲发生器和具有第一W / L比的第一晶体管。脉冲发生器根据在节点处获得的电压提供驱动信号，而第一晶体管保持节点的电压电平。布置在对应的栅极线的第二侧上的第二电路包括具有第二W / L比的第二晶体管。第二晶体管保持来自相应栅极线的第二侧的驱动信号的电压电平。第一W / L比小于第二W / L比，并且第一电路占据比第二电路大的空间。

2. 发明授权

US08223111B2 Display device providing bi-directional voltage stabilization 有权
标题翻译：显示设备提供双向电压稳定
公开(公告)号：US08223111B2
公开(公告)日：2012-07-17
申请号：US12560443
申请日：2009-09-16
申请人： Yi-Suei Liao , Chien-Liang Chen , Ming-Yen Tsai
发明人： Yi-Suei Liao , Chien-Liang Chen , Ming-Yen Tsai
IPC分类号： G09G3/36
CPC分类号： G09G3/3677
摘要： An LCD device includes a plurality of gate lines and a plurality of shift register units for driving corresponding gate lines. Each shift register unit includes a first circuit and a second circuit. The first circuit, disposed on a first side of a corresponding gate line, includes a pulse generator and a first transistor having a first W/L ratio. The pulse generator provides a driving signal according to the voltage obtained at a node, while the first transistor maintains the voltage level of the node. The second circuit, disposed on a second side of the corresponding gate line, includes a second transistor having a second W/L ratio. The second transistor maintains the voltage level of the driving signal from the second side of the corresponding gate line. The first W/L ratio is smaller than the second W/L ratio, and the first circuit occupies larger space than the second circuit.
摘要翻译： LCD装置包括多个栅极线和用于驱动相应的栅极线的多个移位寄存器单元。每个移位寄存器单元包括第一电路和第二电路。布置在对应的栅极线的第一侧上的第一电路包括脉冲发生器和具有第一W / L比的第一晶体管。脉冲发生器根据在节点处获得的电压提供驱动信号，而第一晶体管保持节点的电压电平。布置在对应的栅极线的第二侧上的第二电路包括具有第二W / L比的第二晶体管。第二晶体管保持来自相应栅极线的第二侧的驱动信号的电压电平。第一W / L比小于第二W / L比，并且第一电路占据比第二电路大的空间。

3. 发明授权

US07778379B2 Shift register apparatus 有权
标题翻译：移位寄存器
公开(公告)号：US07778379B2
公开(公告)日：2010-08-17
申请号：US12342042
申请日：2008-12-22
申请人： Yi-Suei Liao , Chien-Liang Chen , Chen-Lun Chiu , Hao-Chieh Lee , Kuan-Yu Chen
发明人： Yi-Suei Liao , Chien-Liang Chen , Chen-Lun Chiu , Hao-Chieh Lee , Kuan-Yu Chen
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof.
摘要翻译：提供一种移位寄存器装置。移位寄存器装置中每个移位寄存器的下拉单元由本身，前一个和下一个两个移位寄存器控制，以增强下拉和电压调节的能力。因此，每个移位寄存器的电路结构不需要在其中设计大的补偿电容器，以基本上抑制由时钟信号引起的耦合噪声效应，并且因此允许每个移位寄存器可以以小的补偿电容器，以提高其输出能力。

4. 发明申请

US20100134234A1 SHIFT REGISTER APPARATUS 有权
标题翻译：移位寄存器
公开(公告)号：US20100134234A1
公开(公告)日：2010-06-03
申请号：US12342042
申请日：2008-12-22
申请人： Yi-Suei Liao , Chien-Liang Chen , Chen-Lun Chiu , Hao-Chieh Lee , Kuan-Yu Chen
发明人： Yi-Suei Liao , Chien-Liang Chen , Chen-Lun Chiu , Hao-Chieh Lee , Kuan-Yu Chen
IPC分类号： G11C19/28
CPC分类号： G11C19/28
摘要： A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof.
摘要翻译：提供一种移位寄存器装置。移位寄存器装置中每个移位寄存器的下拉单元由本身，前一个和下一个两个移位寄存器控制，以增强下拉和电压调节的能力。因此，每个移位寄存器的电路结构不需要在其中设计大的补偿电容器，以基本上抑制由时钟信号引起的耦合噪声效应，并且因此允许每个移位寄存器可以以小的补偿电容器，以提高其输出能力。

5. 发明申请

US20110102310A1 SHIFT REGISTER WITH IMAGE RETENTION RELEASE AND METHOD FOR IMAGE RETENTION RELEASE 有权
标题翻译：具有图像保留释放的移位寄存器和用于图像保留释放的方法
公开(公告)号：US20110102310A1
公开(公告)日：2011-05-05
申请号：US12643963
申请日：2009-12-21
申请人： Chen-Lun Chiu , Hao-Chieh Lee , Yi-Suei Liao , Chien-Liang Chen
发明人： Chen-Lun Chiu , Hao-Chieh Lee , Yi-Suei Liao , Chien-Liang Chen
IPC分类号： G09G3/36 , G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G2310/0205 , G09G2310/0245 , G09G2310/0286 , G09G2320/0257 , G09G2330/027
摘要： A flat panel display, a shift register with image retention release and method for releasing image retention are provided. An output end of the shift register couples to a gate line of a display panel. A first end of a first transistor couples to the output end of the shift register. A second end of the first transistor couples to a system voltage VDD or a reference voltage VSS. A first end of a capacitor couples to a control end of the first transistor. A second end of the capacitor couples to the reference voltage VSS. During a power-off period, the reference voltage VSS is pulled high for turning on the first transistor, therefore the voltage of the gate line is pulled high.
摘要翻译：提供了平板显示器，具有图像保持释放的移位寄存器和用于释放图像保持的方法。移位寄存器的输出端耦合到显示面板的栅极线。第一晶体管的第一端耦合到移位寄存器的输出端。第一晶体管的第二端耦合到系统电压VDD或参考电压VSS。电容器的第一端耦合到第一晶体管的控制端。电容器的第二端耦合到参考电压VSS。在断电期间，参考电压VSS被拉高以接通第一晶体管，因此栅极线的电压被拉高。

6. 发明申请

US20110085098A1 ARRAY SUBSTRATE AND FLAT DISPLAY DEVICE 有权
标题翻译：阵列基板和平面显示设备
公开(公告)号：US20110085098A1
公开(公告)日：2011-04-14
申请号：US12695141
申请日：2010-01-27
申请人： Yi-Suei Liao , Chien-Liang Chen , Kai-Yuan Siao
发明人： Yi-Suei Liao , Chien-Liang Chen , Kai-Yuan Siao
IPC分类号： G02F1/1343 , G09G3/36
CPC分类号： G09G3/3614 , G09G3/3607 , G09G2320/0209
摘要： A flat display device includes an array substrate. The array substrate includes a plurality of gate lines, data lines and pixels. The pixels include a plurality of first pixel units and second pixel units, and each of the first pixel units and each of the second pixel units include more than three pixels. The first pixel units and the second pixel units disposed in between two adjacent data lines are arranged alternately, wherein the first pixel units are electrically connected with one of the two adjacent data lines, and the second pixel units are electrically connected with the other data line.
摘要翻译：平面显示装置包括阵列基板。阵列基板包括多条栅极线，数据线和像素。像素包括多个第一像素单元和第二像素单元，并且第一像素单元和第二像素单元中的每一个包括多于三个像素。设置在两个相邻数据线之间的第一像素单元和第二像素单元交替布置，其中第一像素单元与两个相邻数据线之一电连接，并且第二像素单元与另一数据线电连接。

7. 发明授权

US08497832B2 Shift register with image retention release and method for image retention release 有权
标题翻译：具有图像保留版本的移位寄存器和图像保留版本的方法
公开(公告)号：US08497832B2
公开(公告)日：2013-07-30
申请号：US12643963
申请日：2009-12-21
申请人： Chen-Lun Chiu , Hao-Chieh Lee , Yi-Suei Liao , Chien-Liang Chen
发明人： Chen-Lun Chiu , Hao-Chieh Lee , Yi-Suei Liao , Chien-Liang Chen
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G2310/0205 , G09G2310/0245 , G09G2310/0286 , G09G2320/0257 , G09G2330/027
摘要： A flat panel display, a shift register with image retention release and method for releasing image retention are provided. An output end of the shift register couples to a gate line of a display panel. A first end of a first transistor couples to the output end of the shift register. A second end of the first transistor couples to a system voltage VDD or a reference voltage VSS. A first end of a capacitor couples to a control end of the first transistor. A second end of the capacitor couples to the reference voltage VSS. During a power-off period, the reference voltage VSS is pulled high for turning on the first transistor, therefore the voltage of the gate line is pulled high.
摘要翻译：提供了平板显示器，具有图像保持释放的移位寄存器和用于释放图像保持的方法。移位寄存器的输出端耦合到显示面板的栅极线。第一晶体管的第一端耦合到移位寄存器的输出端。第一晶体管的第二端耦合到系统电压VDD或参考电压VSS。电容器的第一端耦合到第一晶体管的控制端。电容器的第二端耦合到参考电压VSS。在断电期间，参考电压VSS被拉高以接通第一晶体管，因此栅极线的电压被拉高。

8. 发明授权

US08284368B2 Array substrate and flat display device 有权
标题翻译：阵列基板和平板显示装置
公开(公告)号：US08284368B2
公开(公告)日：2012-10-09
申请号：US12695141
申请日：2010-01-27
申请人： Yi-Suei Liao , Chien-Liang Chen , Kai-Yuan Siao
发明人： Yi-Suei Liao , Chien-Liang Chen , Kai-Yuan Siao
IPC分类号： G02F1/1343
CPC分类号： G09G3/3614 , G09G3/3607 , G09G2320/0209
摘要： A flat display device includes an array substrate. The array substrate includes a plurality of gate lines, data lines and pixels. The pixels include a plurality of first pixel units and second pixel units, and each of the first pixel units and each of the second pixel units include more than three pixels. The first pixel units and the second pixel units disposed in between two adjacent data lines are arranged alternately, wherein the first pixel units are electrically connected with one of the two adjacent data lines, and the second pixel units are electrically connected with the other data line.
摘要翻译：平面显示装置包括阵列基板。阵列基板包括多条栅极线，数据线和像素。像素包括多个第一像素单元和第二像素单元，并且第一像素单元和第二像素单元中的每一个包括多于三个像素。设置在两个相邻数据线之间的第一像素单元和第二像素单元交替布置，其中第一像素单元与两个相邻数据线之一电连接，并且第二像素单元与另一数据线电连接。

9. 发明申请

US20160015371A1 Sampling Apparatus 审中-公开
标题翻译：采样仪
公开(公告)号：US20160015371A1
公开(公告)日：2016-01-21
申请号：US14335975
申请日：2014-07-21
申请人： Chien-Liang Chen
发明人： Chien-Liang Chen
IPC分类号： A61B10/02
CPC分类号： A61B10/0266 , A61B2010/0208 , A61B2560/0418
摘要： A sampling apparatus contains: a tubular member, a pressing mechanism, a forcing member, and a movable sampling member. The tubular member includes an inner thread section, an orifice, a stepped shoulder, a first fixing hole, and a second fixing hole. The pressing mechanism includes a press member, a driving member, a resilient element, and an elastic hook. The driving member includes an inserting segment, an aperture, a retaining slot, and a receiving groove, and two ends of the resilient element abut against the driving member and the forcing member. The cylindrical member includes an outer thread section and two opposite positioning recesses. The forcing member includes a needle and two opposite locating stems. The movable sampling member includes a hollowly lower side, a hollow affixing mount, a hollow tool, and a blade.
摘要翻译：采样装置包括：管状构件，按压机构，迫使构件和可动取样构件。管状构件包括内螺纹部分，孔口，阶梯状肩部，第一固定孔和第二固定孔。按压机构包括按压构件，驱动构件，弹性元件和弹性钩。驱动构件包括插入段，孔，保持槽和接收槽，弹性元件的两端抵靠驱动构件和迫动构件。圆柱形构件包括外螺纹部分和两个相对的定位凹槽。强制构件包括针和两个相对的定位杆。可移动取样构件包括中空下侧，中空固定座，中空工具和刀片。

10. 发明申请

US20130099852A1 CHARGE PUMP CIRCUIT WITH LOW CLOCK FEED-THROUGH 有权
标题翻译：充电泵电路采用低时钟馈电
公开(公告)号：US20130099852A1
公开(公告)日：2013-04-25
申请号：US13280366
申请日：2011-10-25
申请人： Chien-Liang Chen , Ya-Nan Mou , Yuan-Hui Chen , Yu-Jen Chang
发明人： Chien-Liang Chen , Ya-Nan Mou , Yuan-Hui Chen , Yu-Jen Chang
IPC分类号： G05F3/02
CPC分类号： H03L7/0893
摘要： A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit.
摘要翻译：电荷泵电路包括第一比较器，PMOS调谐器，第一电流镜，第一NMOS晶体管，第一PMOS开关，NMOS调谐器，第二电流镜，第一PMOS晶体管和第一NMOS开关。第一PMOS开关耦合在PMOS调谐器和第一电流镜的第一输出PMOS晶体管之间，因此形成在第一PMOS开关的栅极和漏极之间的寄生电容器，形成在栅极和源极之间的寄生电容器第一输出PMOS晶体管和形成在第一输出PMOS晶体管的栅极和漏极之间的寄生电容器被等效地串联耦合，降低了PMOS调谐器和电荷泵输出之间的电容，并且减少了时钟馈通和电荷泵电路中的电荷注入效应。

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