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1. 发明授权

US06703663B1 CMOS device using additional implant regions to enhance ESD performance and device manufactured thereby 有权
标题翻译： CMOS器件使用额外的注入区域来增强ESD性能，并由此制造器件
公开(公告)号：US06703663B1
公开(公告)日：2004-03-09
申请号：US09655086
申请日：2000-09-05
申请人： Jian-Hsing Lee , Yi-Hsun Wu , Jian-Ren Shih
发明人： Jian-Hsing Lee , Yi-Hsun Wu , Jian-Ren Shih
IPC分类号： H01L2976
CPC分类号： H01L29/7833 , H01L21/823814 , H01L27/0266 , H01L29/1083
摘要： A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.
摘要翻译：用N阱和P阱形成在半导体衬底上的半导体存储器件的形成方法包括以下步骤。在衬底上形成栅极氧化物层和栅极层的组合，栅极层与衬底中的P阱上的NMOS FET器件的侧壁和N阱上的PMOS FET器件构图成栅极堆叠。在P阱中的N阱和N-轻掺杂的S / D区中形成P-轻掺杂的S / D区。在栅极堆叠的侧壁上形成间隔物。然后在P阱中形成深N轻掺杂的S / D区，并在N阱中形成深P-轻掺杂的S / D区。形成与未来P + S / D位置下方的栅极自对准的重掺杂P ++区域，以与N阱中的间隔物自对准，并形成与未来N + S / D的栅极自对准的重掺杂N ++区域， D点与P阱中的间隔物自对准。

2. 发明授权

US06552372B2 Integrated circuit having improved ESD protection 有权
标题翻译：集成电路具有改进的ESD保护
公开(公告)号：US06552372B2
公开(公告)日：2003-04-22
申请号：US09827194
申请日：2001-04-05
申请人： Yi-Hsun Wu , Jian-Hsing Lee , Shui-Hung Chen , Jian-Ren Shih
发明人： Yi-Hsun Wu , Jian-Hsing Lee , Shui-Hung Chen , Jian-Ren Shih
IPC分类号： H01L2972
CPC分类号： H01L27/0251
摘要： An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive sections of drivers. Better balance of the ESD current flow is achieved by increasing the width and length of nulti-finger channels of semiconductor material defining the gates of the drivers in the active section. Wider, longer gates of the drivers in the active section increase their ability to carry current, thereby resulting in a more symmetrical distribution of ESD current between the active and inactive sections without degrading the IC's normal performance.
摘要翻译：诸如输入 - 输出缓冲器的MOS集成电路通过平衡通过驱动器的有源和非有效部分的ESD电流来改善对静电放电（ESD）的损坏。通过增加限定有源部分中的驱动器的栅极的半导体材料的多指通道的宽度和长度来实现ESD电流的更好的平衡。有源部分的驱动器较长的栅极增加了其承载电流的能力，从而导致有源和非活动部分之间的ESD电流分布更为对称，而不会降低IC的正常性能。

3. 发明授权

US06400542B1 ESD protection circuit for different power supplies 有权
标题翻译： ESD保护电路用于不同电源
公开(公告)号：US06400542B1
公开(公告)日：2002-06-04
申请号：US09882680
申请日：2001-06-18
申请人： Jian-Hsing Lee , Jian-Ren Shih , Yi-Hsun Wu , Jing-Meng Liu
发明人： Jian-Hsing Lee , Jian-Ren Shih , Yi-Hsun Wu , Jing-Meng Liu
IPC分类号： H02H900
CPC分类号： H01L27/0259
摘要： A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal. If the differential voltage exceeds the second clamping voltage level, the second subgroup of Darlington connected transistors turn on and restore the differential voltage to a level less than the second clamping voltage level.
摘要翻译：一种电压钳位电路，当ESD事件在多个分离的电源电压端子之间引起过大的差分电压时，保护具有多个单独的电源电压端子的集成电路免受损坏。电压钳位电路有两个Darlington连接钳位晶体管的子组。达林顿连接的钳位晶体管的第一个子组连接在第一电源电压端子和第二电源电压端子之间。如果差分电压超过第一钳位电压电平，则达林顿连接的钳位晶体管的第一个子组导通，并将第一个差分电压恢复到小于第一钳位电压电平的电平。连接在第二电源端子和第一电源端子之间的达林顿的第二子组连接钳位晶体管。如果差分电压超过第二钳位电压电平，则达林顿连接晶体管的第二个子组导通，并将差分电压恢复到小于第二钳位电压电平的电平。

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