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1. 发明申请

US20080290367A1 Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device 有权
标题翻译：用于与半导体功率器件集成的多级ESD保护电路布局
公开(公告)号：US20080290367A1
公开(公告)日：2008-11-27
申请号：US11804906
申请日：2007-05-21
申请人： Yi Su , Anup Bhalla , Daniel Ng , Wei Wang , Ji Pan
发明人： Yi Su , Anup Bhalla , Daniel Ng , Wei Wang , Ji Pan
IPC分类号： H01L29/76 , H01L21/20
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0696 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a source metal connected to the source region, and a gate metal configured as a metal stripe surrounding a peripheral region of the substrate connected to a gate pad wherein the gate metal and the gate pad are separated from the source metal by a metal gap. The semiconductor power device further includes an ESD protection circuit includes a plurality of doped dielectric regions of opposite conductivity types constituting ESD diodes extending across the metal gap and connected between the gate metal and the source metal on the peripheral region of the substrate.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括连接到源极区的源极金属和栅极金属，该栅极金属被配置为围绕连接到栅极焊盘的衬底的外围区域的金属条，其中栅极金属和栅极焊盘与源极金属分离金属间隙。半导体功率器件还包括ESD保护电路，其包括构成ESD保护二极管的多个相反导电类型的掺杂电介质区域，该ESD二极管延伸穿过金属间隙并且连接在栅极金属和源极金属之间。

2. 发明授权

US08053808B2 Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device 有权
标题翻译：用于与半导体功率器件集成的多级ESD保护电路布局
公开(公告)号：US08053808B2
公开(公告)日：2011-11-08
申请号：US11804906
申请日：2007-05-21
申请人： Yi Su , Anup Bhalla , Daniel Ng , Wei Wang , Ji Pan
发明人： Yi Su , Anup Bhalla , Daniel Ng , Wei Wang , Ji Pan
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0696 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a source metal connected to the source region, and a gate metal configured as a metal stripe surrounding a peripheral region of the substrate connected to a gate pad wherein the gate metal and the gate pad are separated from the source metal by a metal gap. The semiconductor power device further includes an ESD protection circuit includes a plurality of doped polysilicon regions of opposite conductivity types constituting ESD diodes extending across the metal gap and connected between the gate metal and the source metal on the peripheral region of the substrate.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括连接到源极区的源极金属和栅极金属，该栅极金属被配置为围绕连接到栅极焊盘的衬底的外围区域的金属条，其中栅极金属和栅极焊盘与源极金属分离金属间隙。半导体功率器件还包括ESD保护电路，其包括构成ESD保护二极管的相反导电类型的多个掺杂多晶硅区域，该ESD二极管延伸穿过金属间隙并连接在栅极金属与源极金属之间。

3. 发明授权

US08354316B2 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
公开(公告)号：US08354316B2
公开(公告)日：2013-01-15
申请号：US12925820
申请日：2010-10-29
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

4. 发明授权

US07825431B2 Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功能MOSFET的掩模配置
公开(公告)号：US07825431B2
公开(公告)日：2010-11-02
申请号：US12006398
申请日：2007-12-31
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L29/72 , H01L23/62
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

5. 发明申请

US20110076815A1 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功率的MOSFET的掩模配置
公开(公告)号：US20110076815A1
公开(公告)日：2011-03-31
申请号：US12925820
申请日：2010-10-29
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

6. 发明申请

US20090166740A1 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功率的MOSFET的掩模配置
公开(公告)号：US20090166740A1
公开(公告)日：2009-07-02
申请号：US12006398
申请日：2007-12-31
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/06
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

7. 发明申请

US20160315053A1 FLEXIBLE CRSS ADJUSTMENT IN A SGT MOSFET TO SMOOTH WAVEFORMS AND TO AVOID EMI IN DC-DC APPLICATION 有权
公开(公告)号：US20160315053A1
公开(公告)日：2016-10-27
申请号：US14242851
申请日：2014-04-01
申请人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L23/552 , H02M1/44 , H01L29/66 , H02M3/158 , H01L29/40 , H01L29/78
CPC分类号： H01L23/552 , H01L29/0638 , H01L29/401 , H01L29/407 , H01L29/41766 , H01L29/66704 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7823 , H01L29/7825 , H02M1/44 , H02M3/158
摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

8. 发明授权

US08692322B2 Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application 有权
标题翻译： SGT MOSFET中的灵活Crss调整可平滑波形，并避免DC-DC应用中的EMI
公开(公告)号：US08692322B2
公开(公告)日：2014-04-08
申请号：US13539330
申请日：2012-08-26
申请人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
摘要翻译：半导体功率器件包括多个功率晶体管单元，每个功率晶体管单元各自具有设置在栅极沟槽中的沟槽栅极，其中沟槽栅极包括设置在栅极沟槽的底部部分中的屏蔽底部电极，该顶部电极与设置在顶部的顶部栅电极电绝缘栅极沟槽的部分通过电极间绝缘层。晶体管单元中的至少一个包括用作与半导体功率器件的源电极电连接的源极连接屏蔽底部电极的屏蔽底部电极，以及具有用作栅极连接的屏蔽底部电极的至少一个晶体管单元，连接屏蔽底电极，电连接到半导体功率器件的栅极金属。

9. 发明申请

US20130200451A1 NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT 有权
标题翻译： NANO MOSFET，带有TRENCH BOTTOM OXIDE SILIELDED和第三维P-BODY接触
公开(公告)号：US20130200451A1
公开(公告)日：2013-08-08
申请号：US13364948
申请日：2012-02-02
申请人： Hamza Yilmaz , Daniel Ng , Daniel Calafut , Madhur Bobde , Anup Bhalla , Ji Pan , Yeeheng Lee , Jongoh Kim
发明人： Hamza Yilmaz , Daniel Ng , Daniel Calafut , Madhur Bobde , Anup Bhalla , Ji Pan , Yeeheng Lee , Jongoh Kim
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L27/088 , H01L29/0623 , H01L29/0626 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.
摘要翻译：半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。在轻掺杂层中形成一个或多个器件。每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。体区与轻掺杂层和重掺杂层具有相反的导电类型。源区域靠近上表面形成。在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

10. 发明申请

US20130015550A1 JUNCTION BARRIER SCHOTTKY DIODE WITH ENFORCED UPPER CONTACT STRUCTURE AND METHOD FOR ROBUST PACKAGING 有权
标题翻译：具有强化接触结构的结构障碍物肖特基二极管和用于稳定包装的方法
公开(公告)号：US20130015550A1
公开(公告)日：2013-01-17
申请号：US13184488
申请日：2011-07-15
申请人： Anup Bhalla , Ji Pan , Daniel Ng
发明人： Anup Bhalla , Ji Pan , Daniel Ng
IPC分类号： H01L29/872 , H01L21/283
CPC分类号： H01L29/872 , H01L24/05 , H01L29/0619 , H01L29/417 , H01L2924/01029 , H01L2924/12032 , H01L2924/00
摘要： A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.
摘要翻译：公开了一种具有强制上接触结构（EUCS）的半导体结屏障肖特基（JBS-SKY）二极管。参考X-Y-Z坐标，JBS-SKY二极管具有与X-Y平面平行的半导体衬底（SCST）。有源器件区（ACDZ）位于SCST上方，并具有Z方向电流流动的JBS-SKY二极管。外围防护区（PRGZ）在SCST顶部并围绕ACDZ。 ACDZ在ALSS顶部具有活性较低的半导体结构（ALSS）和强制性的上接触结构（EUCS）。 EUC具有向下延伸并与EUCS底部导电的顶部接触金属（TPCM）; 并在TPCM内部嵌入底部支撑结构（EBSS），由硬质材料制成，EBSS向下延伸至EUCS底部。在JBS-SKY二极管封装期间遇到TPCM上的结合力时，EBSS强制EUCS抵抗TPCM的另外潜在的微裂纹，降低JBS-SKY二极管的漏电流。

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