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1. 发明申请

US20090248934A1 INTERRUPT DISPATCHING METHOD IN MULTI-CORE ENVIRONMENT AND MULTI-CORE PROCESSOR 失效
标题翻译：多核环境和多核处理器的中断分配方法
公开(公告)号：US20090248934A1
公开(公告)日：2009-10-01
申请号：US12412286
申请日：2009-03-26
申请人： Yi Ge , ChaoJun Liu , Wen Bo Shen , Yuan Ping
发明人： Yi Ge , ChaoJun Liu , Wen Bo Shen , Yuan Ping
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/505
摘要： Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.
摘要翻译：公开了一种多核处理器环境中的中断调度系统和方法。该处理器包括中断调度器和能够进行中断处理的N个核，其被分成多组核心，其中N是大于1的正整数。该方法响应于到达中断产生令牌; 根据中断，确定要优先用于处理中断的一组核心作为热组; 并将令牌发送到热组，从热组中的第一核心顺序地确定是否满足中断分派终止条件，并且在确定中断满足时将当前核心确定为用于处理中断的响应核心调度终止条件。利用本发明，减少了处理器对中断的响应延迟，从而提供了处理器的优化性能。

2. 发明授权

US07953915B2 Interrupt dispatching method in multi-core environment and multi-core processor 失效
标题翻译：多核环境和多核处理器中的中断调度方式
公开(公告)号：US07953915B2
公开(公告)日：2011-05-31
申请号：US12412286
申请日：2009-03-26
申请人： Yi Ge , ChaoJun Liu , Wen Bo Shen , Yuan Ping
发明人： Yi Ge , ChaoJun Liu , Wen Bo Shen , Yuan Ping
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/505
摘要： Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.
摘要翻译：公开了一种多核处理器环境中的中断调度系统和方法。该处理器包括中断调度器和能够进行中断处理的N个核，其被分成多组核心，其中N是大于1的正整数。该方法响应于到达中断产生令牌; 根据中断，确定要优先用于处理中断的一组核心作为热组; 并将令牌发送到热组，从热组中的第一核心顺序地确定是否满足中断分派终止条件，并且在确定中断满足时将当前核心确定为用于处理中断的响应核心调度终止条件。利用本发明，减少了处理器对中断的响应延迟，从而提供了处理器的优化性能。

3. 发明申请

US20120204082A1 DATA BUS SYSTEM, ITS ENCODER/DECODER AND ENCODING/DECODING METHOD 有权
标题翻译：数据总线系统，其编码器/解码器和编码/解码方法
公开(公告)号：US20120204082A1
公开(公告)日：2012-08-09
申请号：US13446565
申请日：2012-04-13
申请人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
发明人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： G06F11/10
摘要： The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme.
摘要翻译：本申请涉及数据总线系统，其编码器/解码器和编码/解码方法。数据总线编码器包括：总线反转编码器，用于通过根据预定的总线反转编码方案对数据执行总线反转编码来产生编码数据和反转指示信息; 虚拟位组生成器，用于根据预定的代码映射将反转指示信息转换为虚拟位组; 以及用于根据预定的错误检查和校正编码方案为虚拟字生成错误校验码的纠错编码器，其中错误校验位的数目大于在预定的错误校验和校正编码方案中至少一个纠错位的数量，虚拟字包括要输出的数据，对应于数据的虚拟位组，以及至少一个填充位，其被配置为由错误校验和校正编码方案所要求的。

4. 发明申请

US20080288691A1 METHOD AND APPARATUS OF LOCK TRANSACTIONS PROCESSING IN SINGLE OR MULTI-CORE PROCESSOR 审中-公开
标题翻译：单个或多个核心处理器的锁定交易处理方法与装置
公开(公告)号：US20080288691A1
公开(公告)日：2008-11-20
申请号：US12115643
申请日：2008-05-06
申请人： Xiao Yuan Bie , Yi Ge , Zhiyong Liang , Peng Shao , Wen Bo Shen
发明人： Xiao Yuan Bie , Yi Ge , Zhiyong Liang , Peng Shao , Wen Bo Shen
IPC分类号： G06F12/14
CPC分类号： G06F9/526 , G06F2209/521 , G06F2209/522
摘要： The present invention relates to a method and apparatus of lock transactions processing in a single or multi-core processor. An embodiment of the present invention is a processor with one or more processing cores, an address arbitrator, where one or more processing cores are configured to submit a lock transaction request to the address arbitrator corresponding to a specific instruction in response to the execution of the specific instruction. The lock transaction request includes a lock variable address asserted on an address bus. The processor further includes a lock controller for performing lock transaction processing in response to the lock transaction request, and notifying processing result to the processing core from which the lock transaction request was sent. The processor further includes a switching device, coupled to the address arbitrator and the lock controller, for identifying the lock transaction request and notifying the lock transaction request to the lock controller.
摘要翻译：本发明涉及一种在单核或多核处理器中锁交易处理的方法和装置。本发明的实施例是具有一个或多个处理核心的处理器，地址仲裁器，其中一个或多个处理核心被配置为响应于执行该特定指令而向与地址仲裁器相对应的特定指令提交锁交易请求具体说明。锁交易请求包括在地址总线上断言的锁定变量地址。该处理器还包括一个锁定控制器，用于响应锁定事务请求执行锁定事务处理，并将处理结果通知处理核心，锁定事务请求被发送到该处理核心。处理器还包括耦合到地址仲裁器和锁定控制器的交换设备，用于识别锁交易请求并通知锁定控制器的锁定事务请求。

5. 发明授权

US09348406B2 Apparatus and method for activating and shutting down enhanced modules within an activated pipeline stage based on performance requirements and module priority 有权
标题翻译：基于性能要求和模块优先级激活和关闭激活的流水线级中的增强模块的装置和方法
公开(公告)号：US09348406B2
公开(公告)日：2016-05-24
申请号：US13457011
申请日：2012-04-26
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Hua Yong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Hua Yong Wang , Huan Hao Zou
IPC分类号： G06F1/32 , G06F9/30 , G06F11/30 , G06F9/38
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，基本流水线阶段同时被激活，增强的流水线阶段根据工作负载的性能要求被激活或关闭。本发明还公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分成基本流水线级和增强的流水线级，每个流水线级分为基模块和至少一增强型模块，基本模块一直被激活，并且增强模块根据工作负载的性能要求被激活或关闭。

6. 发明申请

US20120210106A1 METHOD OF PROCESSING INSTRUCTIONS IN PIPELINE-BASED PROCESSOR 有权
标题翻译：基于管道处理器的处理指令的方法
公开(公告)号：US20120210106A1
公开(公告)日：2012-08-16
申请号：US13457011
申请日：2012-04-26
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
IPC分类号： G06F9/38
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，基本流水线阶段同时被激活，增强的流水线阶段根据工作负载的性能要求被激活或关闭。本发明还公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分成基本流水线级和增强的流水线级，每个流水线级分为基模块和至少一增强型模块，基本模块一直被激活，并且增强模块根据工作负载的性能要求被激活或关闭。

7. 发明授权

US09563259B2 Apparatus and method for activating and shutting down individual enhanced pipeline stages based on stage priority and performance requirements 有权
标题翻译：基于阶段优先级和性能要求激活和关闭各个增强流水线阶段的装置和方法
公开(公告)号：US09563259B2
公开(公告)日：2017-02-07
申请号：US12357910
申请日：2009-01-22
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
IPC分类号： G06F1/32 , G06F9/30 , G06F11/30 , G06F9/38 , G06F9/48
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种基于流水线的中央处理单元，其特征在于，根据功能，将流水线划分为基本流水线阶段和增强流水线阶段，基础流水线段同时被激活，而增强流水线阶段根据对工作负载的性能要求。本发明还公开了一种基于流水线的中央处理单元，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，每个流水线分段分为基本模块和至少一个增强模块，基模块为激活所有时间，增强模块根据工作负载的性能要求被激活或关闭。

8. 发明申请

US20090193424A1 METHOD OF PROCESSING INSTRUCTIONS IN PIPELINE-BASED PROCESSOR AND CORRESPONDING PROCESSOR 有权
标题翻译：基于管道处理器和相应处理器的处理指令的方法
公开(公告)号：US20090193424A1
公开(公告)日：2009-07-30
申请号：US12357910
申请日：2009-01-22
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
IPC分类号： G06F9/46
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，基本流水线阶段同时被激活，增强的流水线阶段根据工作负载的性能要求被激活或关闭。本发明还公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分成基本流水线级和增强的流水线级，每个流水线级分为基模块和至少一增强型模块，基本模块一直被激活，并且增强模块根据工作负载的性能要求被激活或关闭。

9. 发明授权

US08181101B2 Data bus system, its encoder/decoder and encoding/decoding method 有权
标题翻译：数据总线系统，其编码器/解码器和编码/解码方法
公开(公告)号：US08181101B2
公开(公告)日：2012-05-15
申请号：US12363128
申请日：2009-01-30
申请人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
发明人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
IPC分类号： H03L1/00
CPC分类号： G06F11/10
摘要： The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, the mapping is such that the Hamming distance between any possible value of the virtual bit-group and a reference virtual bit-group which cannot be converted into under the mapping is a fixed value, and not greater than the number of error-correction bits of the error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme.
摘要翻译：本申请涉及数据总线系统，其编码器/解码器和编码/解码方法。数据总线编码器包括：总线反转编码器，用于通过根据预定的总线反转编码方案对数据执行总线反转编码来产生编码数据和反转指示信息; 虚拟位组生成器，用于根据预定的代码映射将反转指示信息转换为虚拟位组; 以及用于根据预定的错误检查和校正编码方案为虚拟字生成错误校验码的纠错编码器，其中错误校验位的数目大于在预定的错误校验和校正编码方案中至少一个纠错位的数量，映射使得虚拟位组的任何可能值和参考虚拟位组之间的汉明距离，其中不能转换成映射为固定值，并且不大于错误校验和校正编码方案的纠错位数，虚拟字包括要输出的数据，虚拟位 - 对应于数据的组，以及被配置为由错误校验和校正编码方案所要求的固定值的至少一个填充位。

10. 发明申请

US20090193319A1 DATA BUS SYSTEM, ITS ENCODER/DECODER AND ENCODING/DECODING METHOD 有权
标题翻译：数据总线系统，其编码器/解码器和编码/解码方法
公开(公告)号：US20090193319A1
公开(公告)日：2009-07-30
申请号：US12363128
申请日：2009-01-30
申请人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
发明人： Wen Bo Shen , Chao-Jun Liu , Yi Ge , Qiang Liu
IPC分类号： H03M13/13 , G06F11/10
CPC分类号： G06F11/10
摘要： The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, the mapping is such that the Hamming distance between any possible value of the virtual bit-group and a reference virtual bit-group which cannot be converted into under the mapping is a fixed value, and not greater than the number of error-correction bits of the error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme.
摘要翻译：本申请涉及数据总线系统，其编码器/解码器和编码/解码方法。数据总线编码器包括：总线反转编码器，用于通过根据预定的总线反转编码方案对数据执行总线反转编码来产生编码数据和反转指示信息; 虚拟位组生成器，用于根据预定的代码映射将反转指示信息转换为虚拟位组; 以及用于根据预定的错误检查和校正编码方案为虚拟字生成错误校验码的纠错编码器，其中错误校验位的数目大于在预定的错误校验和校正编码方案中至少一个纠错位的数量，映射使得虚拟位组的任何可能值和参考虚拟位组之间的汉明距离，其中不能转换成映射为固定值，并且不大于错误校验和校正编码方案的纠错位数，虚拟字包括要输出的数据，虚拟位 - 对应于数据的组，以及被配置为由错误校验和校正编码方案所要求的固定值的至少一个填充位。

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