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1. 发明授权

US07372156B2 Method to fabricate aligned dual damascene openings 有权
标题翻译：制造对准双镶嵌开口的方法
公开(公告)号：US07372156B2
公开(公告)日：2008-05-13
申请号：US11174805
申请日：2005-07-05
申请人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
发明人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
IPC分类号： H01L29/40
CPC分类号： H01L21/76807 , H01L21/76829 , H01L21/76834
摘要： An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.
摘要翻译：对准的双镶嵌开口结构，包括以下。具有形成在其上的金属结构的结构。金属结构上的图案层叠层; 所述层堆叠按升序包括：图案化的底部蚀刻停止层; 图案化的下介电材料层; 图案化的中间蚀刻停止层; 和图案化的中间介电材料层; 下部和中间介电层由相同的材料组成。在图案化的底部蚀刻停止层和图案化的下部介电材料层中的上部沟槽开口; 以及图案化的中间蚀刻停止层和图案化的中间介电材料层中的下通孔开口。下通道开口与上沟槽开口连通。其中上沟槽开口和下通孔开口包括对准的双镶嵌开口。

2. 发明授权

US06967156B2 Method to fabricate aligned dual damascene openings 有权
标题翻译：制造对准双镶嵌开口的方法
公开(公告)号：US06967156B2
公开(公告)日：2005-11-22
申请号：US10690998
申请日：2003-10-22
申请人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
发明人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
IPC分类号： H01L21/4763 , H01L21/768 , H01L29/06
CPC分类号： H01L21/76807 , H01L21/76829 , H01L21/76834
摘要： A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. Simultaneously patterning the patterned middle dielectric material layer using the patterned upper dielectric layer as a mask to form an inchoate upper trench opening; and the lower dielectric material layer using the patterned mask layer and the patterned middle etch stop layer as masks to form an inchoate lower via opening aligned with the inchoate upper trench opening.
摘要翻译：一种形成对准的双镶嵌开口的方法，包括以下顺序步骤。在金属结构上形成层叠。层叠层按升序包括底蚀刻停止层; 下介电材料层; 中间蚀刻停止层; 中间介电材料层; 和上介电层。图案化的掩模层形成在图案化的上介电层上，留下图案化的上介电层的暴露的相对部分。使用图案化掩模层和上介电层的暴露部分作为掩模，将中介电材料层图案化以形成开口。使用图案化的上电介质层作为掩模，同时对图案化的中间介电材料层进行图案化以形成初始上沟槽开口; 并且使用图案化掩模层和图案化的中间蚀刻停止层作为掩模的下部电介质材料层形成与前述上部沟槽开口对准的开口下部通孔。

3. 发明授权

US08358007B2 Integrated circuit system employing low-k dielectrics and method of manufacture thereof 有权
标题翻译：采用低k电介质的集成电路系统及其制造方法
公开(公告)号：US08358007B2
公开(公告)日：2013-01-22
申请号：US12796610
申请日：2010-06-08
申请人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
发明人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/3105 , H01L21/31155 , H01L21/76825 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76859 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.
摘要翻译：集成电路系统的制造方法包括：制造具有集成电路的基板; 在集成电路上施加低K电介质层; 在低K电介质层中形成通孔和沟槽，在集成电路上; 通过化学机械平面化（CMP）工艺形成结构表面; 以及对由CMP工艺引起的用于形成植入层和金属钝化层的直接植入物施加到包括修复损伤的低K电介质层。

4. 发明申请

US20100314763A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING LOW-K DIELECTRICS AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：采用低K电介质的集成电路系统及其制造方法
公开(公告)号：US20100314763A1
公开(公告)日：2010-12-16
申请号：US12796610
申请日：2010-06-08
申请人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
发明人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/3105 , H01L21/31155 , H01L21/76825 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76859 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.
摘要翻译：集成电路系统的制造方法包括：制造具有集成电路的基板; 在集成电路上施加低K电介质层; 在低K电介质层中形成通孔和沟槽，在集成电路上; 通过化学机械平面化（CMP）工艺形成结构表面; 以及对由CMP工艺引起的用于形成植入层和金属钝化层的直接植入物施加到包括修复损伤的低K电介质层。

5. 发明申请

US20130256834A1 BACK-SIDE MOM/MIM DEVICES 有权
标题翻译：背面MOM / MIM设备
公开(公告)号：US20130256834A1
公开(公告)日：2013-10-03
申请号：US13430778
申请日：2012-03-27
申请人： Juan Boon TAN , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
发明人： Juan Boon TAN , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L23/5223 , H01L23/481 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate.
摘要翻译：背面MOM / MIM结构集成在具有前端电路的设备上。实施例包括形成具有与前侧相对的前侧和后侧的基板，所述基板在基板的正面上包括电路; 以及在衬底的背面上形成金属 - 氧化物 - 金属（MOM）电容器，金属 - 绝缘体 - 金属（MIM）电容器或其组合。其他实施例包括在衬底中形成穿硅通孔（TSV），将MOM电容器，MIM电容器或其组合连接到衬底前侧上的电路。

6. 发明授权

US08860185B2 Crack-arresting structure for through-silicon vias 有权
标题翻译：通硅通孔的破裂结构
公开(公告)号：US08860185B2
公开(公告)日：2014-10-14
申请号：US13357960
申请日：2012-01-25
申请人： Shaoning Yuan , Yue Kang Lu , Yeow Kheng Lim , Juan Boon Tan
发明人： Shaoning Yuan , Yue Kang Lu , Yeow Kheng Lim , Juan Boon Tan
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L23/481 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05572 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/014
摘要： The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above. The device also includes a conductive structure positioned at least partially within the perimeter of the crack-arresting structure, and a conductive element extending through an opening in the crack-arresting structure, wherein the conductive element is conductively coupled to the conductive structure.
摘要翻译：本文公开的主题涉及形成在半导体芯片上的结构，其用于至少部分地解决半导体芯片中可能由于存在穿硅通孔（TSV）而导致的热诱导应力和金属化系统开裂问题，以及这可能主要是由于TSV的材料与通常构成半导体芯片的其余部分的半导体材料之间的热膨胀的显着差异。本文公开的一种装置包括基底和位于基底上方的裂缝阻止结构，所述裂缝阻止结构包括多个裂缝阻止元件，并且当从上方观察时具有周边。该装置还包括至少部分地位于裂缝阻止结构的周边内的导电结构，以及延伸穿过裂缝阻止结构中的开口的导电元件，其中导电元件与导电结构导电耦合。

7. 发明授权

US08716856B2 Device with integrated power supply 有权
标题翻译：集成电源设备
公开(公告)号：US08716856B2
公开(公告)日：2014-05-06
申请号：US13565748
申请日：2012-08-02
申请人： Juan Boon Tan , Yeow Kheng Lim , Soh Yun Siah , Wei Liu , Shunqiang Gong
发明人： Juan Boon Tan , Yeow Kheng Lim , Soh Yun Siah , Wei Liu , Shunqiang Gong
IPC分类号： H01L23/52
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/481 , H01L23/58 , H01L2224/16225
摘要： Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through silicon via (TSV) contacts.
摘要翻译：公开了用于形成半导体器件的半导体器件和方法。该半导体器件包括一个管芯。模具包括具有第一和第二主表面的模具基板。半导体器件包括设置在管芯衬底的第二主表面下方的功率模块。电源模块通过硅通孔（TSV）触点电连接到管芯。

8. 发明授权

US08466062B2 TSV backside processing using copper damascene interconnect technology 有权
标题翻译： TSV背面处理采用铜镶嵌互连技术
公开(公告)号：US08466062B2
公开(公告)日：2013-06-18
申请号：US13287220
申请日：2011-11-02
申请人： Yue Kang Lu , Shaoning Yuan , Yeow Kheng Lim , Juan Boon Tan
发明人： Yue Kang Lu , Shaoning Yuan , Yeow Kheng Lim , Juan Boon Tan
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02372 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05552 , H01L2224/05569 , H01L2224/0557 , H01L2224/05572 , H01L2224/13022 , H01L2224/131 , H01L2924/00014 , H01L2924/014
摘要： Generally, the subject matter disclosed herein relates to interconnect structures used for making electrical connections between semiconductor chips in a stacked or 3D chip configuration, and methods for forming the same. One illustrative method disclosed herein includes forming a conductive via element in a semiconductor substrate, wherein the conductive via element is formed from a front side of the semiconductor substrate so as to initially extend a partial distance through the semiconductor substrate. The illustrative method also includes forming a via opening in a back side of the semiconductor substrate to expose a surface of the conductive via element, and filling the via opening with a layer of conductive contact material.
摘要翻译：通常，本文公开的主题涉及用于在堆叠或3D芯片配置中进行半导体芯片之间的电连接的互连结构及其形成方法。本文公开的一种说明性方法包括在半导体衬底中形成导电通孔元件，其中导电通孔元件由半导体衬底的前侧形成，以便首先延伸穿过半导体衬底的部分距离。该说明性方法还包括在半导体衬底的背面形成通孔，以暴露导电通孔元件的表面，并用导电接触材料层填充通孔开口。

9. 发明申请

US20130105968A1 TSV Backside Processing Using Copper Damascene Interconnect Technology 有权
标题翻译：使用铜镶嵌互连技术的TSV背面处理
公开(公告)号：US20130105968A1
公开(公告)日：2013-05-02
申请号：US13287220
申请日：2011-11-02
申请人： Yue Kang Lu , Shaoning Yuan , Yeow Kheng Lim , Juan Boon Tan
发明人： Yue Kang Lu , Shaoning Yuan , Yeow Kheng Lim , Juan Boon Tan
IPC分类号： H01L23/498 , H01L21/768 , H01L21/28
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02372 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05552 , H01L2224/05569 , H01L2224/0557 , H01L2224/05572 , H01L2224/13022 , H01L2224/131 , H01L2924/00014 , H01L2924/014
摘要： Generally, the subject matter disclosed herein relates to interconnect structures used for making electrical connections between semiconductor chips in a stacked or 3D chip configuration, and methods for forming the same. One illustrative method disclosed herein includes forming a conductive via element in a semiconductor substrate, wherein the conductive via element is formed from a front side of the semiconductor substrate so as to initially extend a partial distance through the semiconductor substrate. The illustrative method also includes forming a via opening in a back side of the semiconductor substrate to expose a surface of the conductive via element, and filling the via opening with a layer of conductive contact material.
摘要翻译：通常，本文公开的主题涉及用于在堆叠或3D芯片配置中进行半导体芯片之间的电连接的互连结构及其形成方法。本文公开的一种说明性方法包括在半导体衬底中形成导电通孔元件，其中导电通孔元件由半导体衬底的前侧形成，以便首先延伸穿过半导体衬底的部分距离。该说明性方法还包括在半导体衬底的背面形成通孔，以暴露导电通孔元件的表面，并用导电接触材料层填充通孔开口。

10. 发明申请

US20130277810A1 METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS 审中-公开
标题翻译：通过硅酮形成热沉的方法
公开(公告)号：US20130277810A1
公开(公告)日：2013-10-24
申请号：US13453762
申请日：2012-04-23
申请人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah
发明人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah
IPC分类号： H01L29/02 , H01L21/768
CPC分类号： H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material.
摘要翻译：半导体器件通过从后侧表面延伸到半导体衬底中的硅通孔形成，以改善散热。实施例包括在衬底的背面形成空腔，衬底包括在前表面上的栅叠层，并用导热材料填充空腔。

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