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1. 发明授权

US08358007B2 Integrated circuit system employing low-k dielectrics and method of manufacture thereof 有权
标题翻译：采用低k电介质的集成电路系统及其制造方法
公开(公告)号：US08358007B2
公开(公告)日：2013-01-22
申请号：US12796610
申请日：2010-06-08
申请人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
发明人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/3105 , H01L21/31155 , H01L21/76825 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76859 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.
摘要翻译：集成电路系统的制造方法包括：制造具有集成电路的基板; 在集成电路上施加低K电介质层; 在低K电介质层中形成通孔和沟槽，在集成电路上; 通过化学机械平面化（CMP）工艺形成结构表面; 以及对由CMP工艺引起的用于形成植入层和金属钝化层的直接植入物施加到包括修复损伤的低K电介质层。

2. 发明申请

US20100314763A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING LOW-K DIELECTRICS AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：采用低K电介质的集成电路系统及其制造方法
公开(公告)号：US20100314763A1
公开(公告)日：2010-12-16
申请号：US12796610
申请日：2010-06-08
申请人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
发明人： Dong Kyun Sohn , Wuping Liu , Fan Zhang , Juan Boon Tan , Jing Hui Li , Bei Chao Zhang , Luying Du , Wei Liu , Yeow Kheng Lim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/3105 , H01L21/31155 , H01L21/76825 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L21/76859 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.
摘要翻译：集成电路系统的制造方法包括：制造具有集成电路的基板; 在集成电路上施加低K电介质层; 在低K电介质层中形成通孔和沟槽，在集成电路上; 通过化学机械平面化（CMP）工艺形成结构表面; 以及对由CMP工艺引起的用于形成植入层和金属钝化层的直接植入物施加到包括修复损伤的低K电介质层。

3. 发明授权

US07372156B2 Method to fabricate aligned dual damascene openings 有权
标题翻译：制造对准双镶嵌开口的方法
公开(公告)号：US07372156B2
公开(公告)日：2008-05-13
申请号：US11174805
申请日：2005-07-05
申请人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
发明人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
IPC分类号： H01L29/40
CPC分类号： H01L21/76807 , H01L21/76829 , H01L21/76834
摘要： An aligned dual damascene opening structure, comprising the following. A structure having a metal structure formed thereover. A patterned layer stack over the metal structure; the layer stack comprising, in ascending order: a patterned bottom etch stop layer; a patterned lower dielectric material layer; a patterned middle etch stop layer; and a patterned middle dielectric material layer; the lower and middle dielectric layers being comprised of the same material. An upper trench opening in the patterned bottom etch stop layer and the patterned lower dielectric material layer; and a lower via opening in the patterned middle etch stop layer and the patterned middle dielectric material layer. The lower via opening being in communication with the upper trench opening. Wherein the upper trench opening and the lower via opening comprise an aligned dual damascene opening.
摘要翻译：对准的双镶嵌开口结构，包括以下。具有形成在其上的金属结构的结构。金属结构上的图案层叠层; 所述层堆叠按升序包括：图案化的底部蚀刻停止层; 图案化的下介电材料层; 图案化的中间蚀刻停止层; 和图案化的中间介电材料层; 下部和中间介电层由相同的材料组成。在图案化的底部蚀刻停止层和图案化的下部介电材料层中的上部沟槽开口; 以及图案化的中间蚀刻停止层和图案化的中间介电材料层中的下通孔开口。下通道开口与上沟槽开口连通。其中上沟槽开口和下通孔开口包括对准的双镶嵌开口。

4. 发明授权

US06967156B2 Method to fabricate aligned dual damascene openings 有权
标题翻译：制造对准双镶嵌开口的方法
公开(公告)号：US06967156B2
公开(公告)日：2005-11-22
申请号：US10690998
申请日：2003-10-22
申请人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
发明人： Yeow Kheng Lim , Wuping Liu , Tae Jong Lee , Bei Chao Zhang , Juan Boon Tan , Alan Cuthbertson , Chin Chuan Neo
IPC分类号： H01L21/4763 , H01L21/768 , H01L29/06
CPC分类号： H01L21/76807 , H01L21/76829 , H01L21/76834
摘要： A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks. Simultaneously patterning the patterned middle dielectric material layer using the patterned upper dielectric layer as a mask to form an inchoate upper trench opening; and the lower dielectric material layer using the patterned mask layer and the patterned middle etch stop layer as masks to form an inchoate lower via opening aligned with the inchoate upper trench opening.
摘要翻译：一种形成对准的双镶嵌开口的方法，包括以下顺序步骤。在金属结构上形成层叠。层叠层按升序包括底蚀刻停止层; 下介电材料层; 中间蚀刻停止层; 中间介电材料层; 和上介电层。图案化的掩模层形成在图案化的上介电层上，留下图案化的上介电层的暴露的相对部分。使用图案化掩模层和上介电层的暴露部分作为掩模，将中介电材料层图案化以形成开口。使用图案化的上电介质层作为掩模，同时对图案化的中间介电材料层进行图案化以形成初始上沟槽开口; 并且使用图案化掩模层和图案化的中间蚀刻停止层作为掩模的下部电介质材料层形成与前述上部沟槽开口对准的开口下部通孔。

5. 发明授权

US09147654B2 Integrated circuit system employing alternating conductive layers 有权
标题翻译：采用交替导电层的集成电路系统
公开(公告)号：US09147654B2
公开(公告)日：2015-09-29
申请号：US12168816
申请日：2008-07-07
申请人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
发明人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
IPC分类号： H01L23/48 , H01L21/4763 , H01L23/522
CPC分类号： H01L23/5223 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.
摘要翻译：一种集成电路系统，包括：提供包括前端电路的基板; 形成包括在所述衬底上的第一导电迹线的第一导电电平; 形成与所述第一导电电平间隔开并包括第二导电迹线的第二导电电平; 以及将第一导电电平与通过第二导电电平而不接触第二导电迹线的viabar连接到第三导电电平。

6. 发明申请

US20100001370A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS 有权
标题翻译：集成电路系统采用替代导电层
公开(公告)号：US20100001370A1
公开(公告)日：2010-01-07
申请号：US12168816
申请日：2008-07-07
申请人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
发明人： Haifeng Sheng , Fan Zhang , Juan Boon Tan , Bei Chao Zhang , Dong Kyun Sohn
IPC分类号： H01L21/768 , H01L21/02 , H01L27/06
CPC分类号： H01L23/5223 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.
摘要翻译：一种集成电路系统，包括：提供包括前端电路的基板; 形成包括在所述衬底上的第一导电迹线的第一导电电平; 形成与所述第一导电电平间隔开并包括第二导电迹线的第二导电电平; 以及将第一导电电平与通过第二导电电平而不接触第二导电迹线的viabar连接到第三导电电平。

7. 发明授权

US09490165B2 Reliable interconnect integration scheme 有权
标题翻译：可靠的互连集成方案
公开(公告)号：US09490165B2
公开(公告)日：2016-11-08
申请号：US12982862
申请日：2010-12-30
申请人： Luying Du , Fan Zhang , Jun Chen , Bei Chao Zhang , Juan Boon Tan
发明人： Luying Du , Fan Zhang , Jun Chen , Bei Chao Zhang , Juan Boon Tan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/7682 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.
摘要翻译：实施例涉及通过制备具有电介质层的衬底来形成可靠互连的方法，处理介电层以用作IMD层，其中IMD层包括具有不同k值的多个介电材料的混合IMD层。

8. 发明授权

US07276440B2 Method of fabrication of a die oxide ring 有权
标题翻译：芯片氧化物环的制造方法
公开(公告)号：US07276440B2
公开(公告)日：2007-10-02
申请号：US10734423
申请日：2003-12-12
申请人： Fan Zhang , Bei Chao Zhang , Wuping Liu , Kho Liep Chok , Liang Choo Hsia , Tae Jong Lee , Juan Boon Tan , Xian Bin Wang
发明人： Fan Zhang , Bei Chao Zhang , Wuping Liu , Kho Liep Chok , Liang Choo Hsia , Tae Jong Lee , Juan Boon Tan , Xian Bin Wang
IPC分类号： H01L23/04
CPC分类号： H01L23/562 , H01L23/3178 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.
摘要翻译：根据本发明的目的，以“氧化物环”的形式提供了一种用于实施本发明的新设计和方法。传统的模具设置有保护环或密封环，其围绕并隔离单个半导体管芯的有源表面积。本发明的“氧化物环”围绕保护环或密封环，并以这种方式形成在管芯的锯切路径和单个化的半导体管芯的有源表面区域之间的机械应力释放缓冲器。

9. 发明授权

US06995087B2 Integrated circuit with simultaneous fabrication of dual damascene via and trench 有权
标题翻译：集成电路，同时制造双镶嵌通孔和沟槽
公开(公告)号：US06995087B2
公开(公告)日：2006-02-07
申请号：US10328512
申请日：2002-12-23
申请人： Wuping Liu , Juan Boon Tan , Bei Chao Zhang , Alan Cuthbertson
发明人： Wuping Liu , Juan Boon Tan , Bei Chao Zhang , Alan Cuthbertson
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76811 , H01L21/76813
摘要： An integrated circuit manufacturing method includes providing a base, forming a first conductor, forming a first barrier layer, forming a first dielectric layer, and forming a masking layer. The method further including forming a first via opening in the masking layer, forming a first trench opening in the masking layer, and simultaneously forming a second via opening in a layer under the masking layer, and forming a second trench opening through the masking layer and in the layer under the masking layer and simultaneously forming a third via opening in another layer under the masking layer. The method further including removing the first barrier layer using the third via opening and the masking layer to form a trench and a via, and filling the trench and the via with a conductor to form a trench and via conductor in contact with the first conductor.
摘要翻译：集成电路制造方法包括提供基底，形成第一导体，形成第一阻挡层，形成第一介电层，形成掩模层。该方法还包括在掩模层中形成第一通孔，在掩模层中形成第一沟槽开口，同时在掩模层下方的层中形成第二通孔，并形成穿过掩模层的第二沟槽开口，在掩模层下面的层中并且同时在掩模层下方的另一层中形成第三通孔。该方法还包括使用第三通孔开口和掩模层去除第一阻挡层以形成沟槽和通孔，以及用导体填充沟槽和通孔以形成与第一导体接触的沟槽和通孔导体。

10. 发明授权

US08716856B2 Device with integrated power supply 有权
标题翻译：集成电源设备
公开(公告)号：US08716856B2
公开(公告)日：2014-05-06
申请号：US13565748
申请日：2012-08-02
申请人： Juan Boon Tan , Yeow Kheng Lim , Soh Yun Siah , Wei Liu , Shunqiang Gong
发明人： Juan Boon Tan , Yeow Kheng Lim , Soh Yun Siah , Wei Liu , Shunqiang Gong
IPC分类号： H01L23/52
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/481 , H01L23/58 , H01L2224/16225
摘要： Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through silicon via (TSV) contacts.
摘要翻译：公开了用于形成半导体器件的半导体器件和方法。该半导体器件包括一个管芯。模具包括具有第一和第二主表面的模具基板。半导体器件包括设置在管芯衬底的第二主表面下方的功率模块。电源模块通过硅通孔（TSV）触点电连接到管芯。

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