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1. 发明授权

US06558994B2 Dual silicon-on-insulator device wafer die 失效
公开(公告)号：US06558994B2
公开(公告)日：2003-05-06
申请号：US09841564
申请日：2001-03-01
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/76278 , H01L21/76281 , H01L21/76283 , H01L2924/0002 , Y10S438/967 , H01L2924/00
摘要： A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

2. 发明授权

US06849928B2 Dual silicon-on-insulator device wafer die 失效
标题翻译：双硅绝缘体上硅器件芯片
公开(公告)号：US06849928B2
公开(公告)日：2005-02-01
申请号：US10327309
申请日：2002-12-19
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L21/762 , H01L23/28
CPC分类号： H01L21/76264 , H01L21/76278 , H01L21/76281 , H01L21/76283 , H01L2924/0002 , Y10S438/967 , H01L2924/00
摘要： A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.
摘要翻译：提供一种绝缘体上半导体器件，其中单个晶片管芯在绝缘体层上包含晶体管以形成完全耗尽的绝缘体上硅器件，并且在半导体晶片上的绝缘体结构上形成半导体岛中的晶体管形成部分耗尽的绝缘体上硅器件。

3. 发明授权

US06613652B2 Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance 失效
公开(公告)号：US06613652B2
公开(公告)日：2003-09-02
申请号：US09805707
申请日：2001-03-14
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L2130
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76289 , H01L21/764 , H01L27/12
摘要： A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

4. 发明授权

US06468880B1 Method for fabricating complementary silicon on insulator devices using wafer bonding 失效
标题翻译：使用晶片接合制造绝缘体上互补硅的方法
公开(公告)号：US06468880B1
公开(公告)日：2002-10-22
申请号：US09805954
申请日：2001-03-15
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L2130
CPC分类号： H01L21/76264 , H01L21/76283 , H01L21/84 , Y10S438/977
摘要： A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions. Next, the stop layer is removed. Lastly, devices are formed in and on the active regions.
摘要翻译：一种使用晶片接合形成绝缘体上硅（SOI）器件的方法。提供第一基板，其在第一侧上具有绝缘层。提供了第二衬底，其具有填充第二衬底中的第一沟槽的第一隔离区域（例如STI）。接下来，通过将绝缘层粘合到第一隔离区域和第二基板上，将第一和第二基板结合在一起。然后，在第二基板的第二侧上形成止挡层。图案化第二基板的阻挡层和第二侧，以在第二基板中形成第二沟槽。第二沟槽具有由隔离区域至少部分地限定的侧壁，并且第二沟槽露出第二绝缘层。第二沟槽限定第一隔离区域（STI）上的第一有源区，并在绝缘层上限定第二有源区。接下来，第二沟槽用绝缘体材料填充到第二隔离区域。接下来，停止层被去除。最后，在活动区域中形成器件。

5. 发明授权

US08766454B2 Integrated circuit with self-aligned line and via 有权
标题翻译：具有自对准线和通孔的集成电路
公开(公告)号：US08766454B2
公开(公告)日：2014-07-01
申请号：US11466018
申请日：2006-08-21
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
IPC分类号： H01L23/48 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.
摘要翻译：提供一种集成电路，其具有形成在其上的第一电介质层的基极。在第一电介质层上形成第二电介质层。第三电介质层形成在第二电介质层上的间隔开的条带中。第一沟槽开口通过第三和第二电介质层形成在第三介电层间隔开的条之间。第二沟槽开口与通过第一介电层的第一沟槽开口连续地形成在第三介电层的间隔开的条之间。沟槽开口中的导体金属形成自对准沟槽互连。

6. 发明授权

US07119010B2 Integrated circuit with self-aligned line and via and manufacturing method therefor 有权
公开(公告)号：US07119010B2
公开(公告)日：2006-10-10
申请号：US10128875
申请日：2002-04-23
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

7. 发明授权

US06472697B2 Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application 有权
公开(公告)号：US06472697B2
公开(公告)日：2002-10-29
申请号：US10140574
申请日：2002-05-08
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh , Victor Seng Keong Lim
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh , Victor Seng Keong Lim
IPC分类号： H01L2710
CPC分类号： H01L21/76838 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

8. 发明授权

US06399471B1 Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application 失效
公开(公告)号：US06399471B1
公开(公告)日：2002-06-04
申请号：US09783379
申请日：2001-02-15
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh , Victor Seng Keong Lim
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh , Victor Seng Keong Lim
IPC分类号： H01L2144
CPC分类号： H01L21/76838 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

9. 发明授权

US06380084B1 Method to form high performance copper damascene interconnects by de-coupling via and metal line filling 有权
标题翻译：通过去耦合通孔和金属线填充形成高性能铜镶嵌互连的方法
公开(公告)号：US06380084B1
公开(公告)日：2002-04-30
申请号：US09678621
申请日：2000-10-02
申请人： Yeow Kheng Lim , Alex See , Cher Liang Cha , Subhash Gupta , Wang Ling Goh , Man Siu Tse
发明人： Yeow Kheng Lim , Alex See , Cher Liang Cha , Subhash Gupta , Wang Ling Goh , Man Siu Tse
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/32051 , H01L21/76802 , H01L21/76849 , H01L21/7685 , H01L21/76877 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches. The third barrier layer and the via caps are etched to form trench barrier sidewall spacers and to expose the vias. The connective line trenches are filled with a second copper layer by a single deposition, by a first deposition of a seed layer followed by plating, or by plating using the via as the seed layer. The second copper layer is polished down.
摘要翻译：已经实现了通过解耦通孔和连接线沟槽填充形成鲁棒的双镶嵌互连的方法。沉积在氮化硅层上的第一介电层。屏蔽层被沉积。将屏蔽层，第一介电层和氮化硅层图案化以形成通孔沟槽。沉积第一势垒层以对沟槽进行排列。通过单个沉积或通过沉积种子层然后进行无电镀或电化学电镀，将通孔沟槽填充有第一铜层。第一个铜层被抛光以完成通孔。沉积第二阻挡层。图案化第二阻挡层以形成通孔。沉积第二介电层。沉积覆盖层。图案化覆盖层和第二介电层以形成连接线沟槽，其暴露通孔盖的一部分。沉积第三阻挡层以对连接线沟槽进行排列。蚀刻第三阻挡层和通孔盖以形成沟槽阻挡侧壁间隔件并露出通孔。连接线沟槽通过单次沉积，通过第一次沉积种子层，然后电镀，或通过使用通孔作为种子层进行电镀，填充第二铜层。第二个铜层被抛光。

10. 发明授权

US06613649B2 Method for buffer STI scheme with a hard mask layer as an oxidation barrier 有权
标题翻译：具有硬掩模层作为氧化屏障的缓冲STI方案
公开(公告)号：US06613649B2
公开(公告)日：2003-09-02
申请号：US10002873
申请日：2001-12-05
申请人： Seng-Keong Victor Lim , Feng Chen , Alex See , Wang Ling Goh
发明人： Seng-Keong Victor Lim , Feng Chen , Alex See , Wang Ling Goh
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of manufacturing a shallow trench isolation using a polishing step with reduced dishing. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We etch a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trench in the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer using a thermal oxidation. The hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves the buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed at least partially filling the trench. The insulating layer is chemical-mechanical polished using the polish stop layer as a stop layer. The buffer layer acts to prevent field oxide dishing during the chemical-mechanical polish.
摘要翻译：使用具有减少的凹陷的抛光步骤制造浅沟槽隔离的方法。在衬底上形成焊盘层，抛光停止层，缓冲层和硬掩模层。硬掩模层具有硬掩模开口。我们使用硬掩模层作为蚀刻掩模，在缓冲层，抛光停止层，焊盘层中蚀刻沟槽开口，并在衬底中形成沟槽。我们使用热氧化沿着沟槽的侧壁和缓冲层的侧壁上的氧化物缓冲衬垫层形成氧化物沟槽衬里层。硬掩模层防止在氧化物沟槽衬垫的氧化期间缓冲层的顶表面的氧化。这防止缓冲层被氧化消耗，并使缓冲层在随后的化学 - 机械抛光（CMP）步骤中起作用。接下来，形成至少部分地填充沟槽的绝缘层。绝缘层使用抛光停止层作为停止层进行化学机械抛光。缓冲层用于防止化学机械抛光过程中的场氧化物凹陷。

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