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1. 发明申请

US20130256874A1 Elongated Bumps in Integrated Circuit Devices 有权
标题翻译：集成电路器件中的伸长的冲击波
公开(公告)号：US20130256874A1
公开(公告)日：2013-10-03
申请号：US13559840
申请日：2012-07-27
申请人： Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
发明人： Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
IPC分类号： H01L23/498
CPC分类号： H01L23/3192 , H01L23/293 , H01L23/49811 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05005 , H01L2224/05015 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/13012 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/00014 , H01L2924/01029 , H01L2924/00012 , H01L2924/206 , H01L2924/01047
摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.
摘要翻译：一种器件包括衬底，衬底上的金属焊盘以及覆盖金属焊盘的边缘部分的钝化层。钝化层具有与金属焊盘重叠的第一开口，其中第一开口具有在平行于衬底的主表面的方向上测量的第一横向尺寸。聚合物层在钝化层上方并覆盖金属焊盘的边缘部分。聚合物层具有与金属垫重叠的第二开口。第二开口具有在该方向上测量的第二横向尺寸。第一横向尺寸大于第二横向尺寸大于约7μm。下冲击冶金（UBM）包括第二开口中的第一部分和覆盖聚合物层部分的第二部分。

2. 发明授权

US08922006B2 Elongated bumps in integrated circuit devices 有权
标题翻译：集成电路设备中的延长凸块
公开(公告)号：US08922006B2
公开(公告)日：2014-12-30
申请号：US13559840
申请日：2012-07-27
申请人： Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
发明人： Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
IPC分类号： H01L23/488
CPC分类号： H01L23/3192 , H01L23/293 , H01L23/49811 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05005 , H01L2224/05015 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/13012 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/00014 , H01L2924/01029 , H01L2924/00012 , H01L2924/206 , H01L2924/01047
摘要： A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.
摘要翻译：一种器件包括衬底，衬底上的金属焊盘以及覆盖金属焊盘的边缘部分的钝化层。钝化层具有与金属焊盘重叠的第一开口，其中第一开口具有在平行于衬底的主表面的方向上测量的第一横向尺寸。聚合物层在钝化层上方并覆盖金属焊盘的边缘部分。聚合物层具有与金属垫重叠的第二开口。第二开口具有在该方向上测量的第二横向尺寸。第一横向尺寸大于第二横向尺寸大于约7μm。下冲击冶金（UBM）包括第二开口中的第一部分和覆盖聚合物层部分的第二部分。

3. 发明授权

US08643196B2 Structure and method for bump to landing trace ratio 有权
标题翻译：撞击到达轨迹比的结构和方法
公开(公告)号：US08643196B2
公开(公告)日：2014-02-04
申请号：US13426386
申请日：2012-03-21
申请人： Chen-Hua Yu , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Sheng-Yu Wu , Yen-Liang Lin
发明人： Chen-Hua Yu , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Sheng-Yu Wu , Yen-Liang Lin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/49811 , H01L21/76885 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L2224/1145 , H01L2224/1146 , H01L2224/13005 , H01L2224/13012 , H01L2224/13014 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13147 , H01L2224/16238 , H01L2924/1306 , H01L2924/00014 , H01L2924/00012 , H01L2924/206 , H01L2924/00
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.
摘要翻译：本发明提供集成电路。集成电路包括形成在基板上的互连结构; 形成在所述互连结构上并联接到所述互连结构的着陆金属迹线，其中所述着陆金属迹线包括沿第一方向限定的第一宽度T; 以及形成在所述着陆金属迹线上并与所述着陆金属迹线对准的金属凸块柱，其中所述金属凸块柱包括在所述第一方向上限定的第二宽度U，并且所述第二宽度U大于所述第一宽度T.

4. 发明申请

US20130026614A1 STRUCTURE AND METHOD FOR BUMP TO LANDING TRACE RATIO 有权
标题翻译：结构和方法，用于防止爬坡比例
公开(公告)号：US20130026614A1
公开(公告)日：2013-01-31
申请号：US13426386
申请日：2012-03-21
申请人： Chen-Hua Yu , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Sheng-Yu Wu , Yen-Liang Lin
发明人： Chen-Hua Yu , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Sheng-Yu Wu , Yen-Liang Lin
IPC分类号： H01L23/495 , H01L21/98
CPC分类号： H01L23/49811 , H01L21/76885 , H01L23/49816 , H01L24/13 , H01L24/16 , H01L2224/1145 , H01L2224/1146 , H01L2224/13005 , H01L2224/13012 , H01L2224/13014 , H01L2224/13017 , H01L2224/13082 , H01L2224/13083 , H01L2224/13147 , H01L2224/16238 , H01L2924/1306 , H01L2924/00014 , H01L2924/00012 , H01L2924/206 , H01L2924/00
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.
摘要翻译：本发明提供集成电路。集成电路包括形成在基板上的互连结构; 形成在所述互连结构上并联接到所述互连结构的着陆金属迹线，其中所述着陆金属迹线包括沿第一方向限定的第一宽度T; 以及形成在所述着陆金属迹线上并与所述着陆金属迹线对准的金属凸块柱，其中所述金属凸块柱包括在所述第一方向上限定的第二宽度U，并且所述第二宽度U大于所述第一宽度T.

5. 发明授权

US08853853B2 Bump structures 有权
标题翻译：凹凸结构
公开(公告)号：US08853853B2
公开(公告)日：2014-10-07
申请号：US13192302
申请日：2011-07-27
申请人： Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen , Yen-Liang Lin
发明人： Chih-Horng Chang , Tin-Hao Kuo , Chen-Shien Chen , Yen-Liang Lin
IPC分类号： H01L23/48
CPC分类号： H01L24/16 , H01L24/13 , H01L24/81 , H01L2224/0401 , H01L2224/05572 , H01L2224/05599 , H01L2224/10145 , H01L2224/13012 , H01L2224/13015 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/16238 , H01L2224/81191 , H01L2224/81815 , H01L2924/00014 , H01L2924/01322 , Y10T428/12493 , Y10T428/24479 , H01L2924/014 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： The embodiments of bump and bump-on-trace (BOT) structures provide bumps with recess regions for reflowed solder to fill. The recess regions are placed in areas of the bumps where reflow solder is most likely to protrude. The recess regions reduce the risk of bump to trace shorting. As a result, yield can be improved.
摘要翻译：凸块和凸块（BOT）结构的实施例提供具有用于回填焊料填充的凹陷区域的凸块。凹陷区域放置在凸起焊接区域最可能突出的区域。凹陷区域减少了跟踪短路的风险。结果，可以提高收率。

6. 发明申请

US20130277828A1 Methods and Apparatus for bump-on-trace Chip Packaging 审中-公开
标题翻译：贴片跟踪芯片封装的方法和装置
公开(公告)号：US20130277828A1
公开(公告)日：2013-10-24
申请号：US13450191
申请日：2012-04-18
申请人： Chang-Chia Huang , Tsung-Shu Lin , Han-Ping Pu , Yen-Liang Lin , Sheng-Hsiang Chiu
发明人： Chang-Chia Huang , Tsung-Shu Lin , Han-Ping Pu , Yen-Liang Lin , Sheng-Hsiang Chiu
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L24/16 , H01L23/49816 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16237 , H01L2224/16238 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81024 , H01L2224/81191 , H01L2224/81815 , H01L2224/83102 , H01L2924/15311 , H01L2224/16225 , H01L2924/00 , H01L2924/00014 , H01L2924/0665
摘要： Methods and apparatus for a solder mask trench used in a bump-on-trace (BOT) structure to form a semiconductor package are disclosed. A solder mask layer is formed on a trace and on a substrate. An opening of the solder mask layer, called a solder mask trench, is formed to expose the trace on the substrate. The solder mask trench has a width about a size of a diameter of a solder bump. A solder bump is landed directly on the exposed trace to connect a chip to the trace by an interconnect. With the formation of the solder mask trench, the trace exposed in the solder mask trench have a better grab force, which reduces the trace peeling failure for the semiconductor package. A plurality of solder mask trench rings may be formed in a package.
摘要翻译：公开了用于形成半导体封装的凸起跟踪（BOT）结构中的焊接掩模沟槽的方法和装置。在迹线和基板上形成焊料掩模层。形成焊料掩模层的开口，称为焊料掩模沟槽，以露出衬底上的迹线。焊接掩模沟槽的宽度大约为焊料凸块的直径。焊料凸块直接落在裸露的轨迹上，通过互连将芯片连接到轨迹。通过焊接掩模沟槽的形成，在焊接掩模沟槽中暴露的迹线具有更好的抓取力，这减少了半导体封装的迹线剥离故障。可以在封装中形成多个焊接掩模沟槽环。

7. 发明授权

US09219106B2 Integrated inductor 有权
标题翻译：集成电感
公开(公告)号：US09219106B2
公开(公告)日：2015-12-22
申请号：US13198783
申请日：2011-08-05
申请人： Yen-Liang Lin , Mirng-Ji Lii , Chen-Shien Chen , Ching-Wen Hsiao , Tsung-Ding Wang
发明人： Yen-Liang Lin , Mirng-Ji Lii , Chen-Shien Chen , Ching-Wen Hsiao , Tsung-Ding Wang
IPC分类号： H01L27/08 , H01L49/02 , H01L23/522 , H01L23/00
CPC分类号： H01L28/10 , H01L23/5227 , H01L24/05 , H01L24/13 , H01L2224/0346 , H01L2224/0401 , H01L2224/05024 , H01L2224/05147 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05572 , H01L2224/05649 , H01L2224/05655 , H01L2224/05657 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13006 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/01029 , H01L2924/00014 , H01L2924/014 , H01L2924/0103 , H01L2924/01083
摘要： A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.
摘要翻译：提供了一种用于提供具有高质量因子（Q）的集成电感器的系统和方法。一个实施例包括位于导电螺旋中心的磁芯。磁芯增加了集成电感器的电感，使得电感器可用于诸如RF扼流圈的应用中。磁芯可以以与下凸缘金属化相同的方式和时间形成。

8. 发明申请

US20130032923A1 Integrated Inductor 有权
标题翻译：集成电感
公开(公告)号：US20130032923A1
公开(公告)日：2013-02-07
申请号：US13198783
申请日：2011-08-05
申请人： Yen-Liang Lin , Mirng-Ji Lii , Chen-Shien Chen , Ching-Wen Hsiao , Tsung-Ding Wang
发明人： Yen-Liang Lin , Mirng-Ji Lii , Chen-Shien Chen , Ching-Wen Hsiao , Tsung-Ding Wang
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L28/10 , H01L23/5227 , H01L24/05 , H01L24/13 , H01L2224/0346 , H01L2224/0401 , H01L2224/05024 , H01L2224/05147 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05572 , H01L2224/05649 , H01L2224/05655 , H01L2224/05657 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13006 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/01029 , H01L2924/00014 , H01L2924/014 , H01L2924/0103 , H01L2924/01083
摘要： A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.
摘要翻译：提供了一种用于提供具有高质量因子（Q）的集成电感器的系统和方法。一个实施例包括位于导电螺旋中心的磁芯。磁芯增加了集成电感器的电感，使得电感器可用于诸如RF扼流圈的应用中。磁芯可以以与下凸缘金属化相同的方式和时间形成。

9. 发明申请

US20080253344A1 Wireless LAN medium access controller supporting mode change and mode change method therreof 审中-公开
标题翻译：无线局域网介质访问控制器支持模式更改和模式更改方法
公开(公告)号：US20080253344A1
公开(公告)日：2008-10-16
申请号：US12213216
申请日：2008-06-17
申请人： Yen-Liang Lin , Hsung-Pin Chang , Ruei-Chuan Chang
发明人： Yen-Liang Lin , Hsung-Pin Chang , Ruei-Chuan Chang
IPC分类号： H04Q7/24
CPC分类号： H04W36/14 , H04W36/0011 , H04W88/06 , Y02D70/142
摘要： A wireless LAN medium access controller supporting mode change and the mode change method thereof are proposed. A physical layer detects signal strength in the environment and writes a mode index value of the stronger signal into a register. When the written mode index value is different from a mode index value in the communication system, a medium access controller is informed to perform mode change. The physical layer then sends out an interrupt signal to a central processor and sends the mode index value to the central processor for comparison via a DMA module and a memory. An interface module is used to access the mode index value in the memory for providing an external interface for the medium access control layer. When the mode index value doesn't conform to the signal in the environment, a software layer in the medium access controller is used for mode change.
摘要翻译：提出了一种支持模式变化的无线局域网媒体接入控制器及其模式变化方法。物理层检测环境中的信号强度，并将较强信号的模式索引值写入寄存器。当写入模式索引值与通信系统中的模式索引值不同时，通知媒体访问控制器执行模式改变。物理层然后向中央处理器发出中断信号，并将模式索引值发送到中央处理器，以通过DMA模块和存储器进行比较。接口模块用于访问存储器中的模式索引值，以为介质访问控制层提供外部接口。当模式索引值不符合环境中的信号时，介质访问控制器中的软件层用于模式更改。

10. 发明申请

US20120306390A1 Architecture for Supporting Modulized Full Operation Junction Ultra High Voltage (UHV) Light Emitting Diode (LED) Device 审中-公开
标题翻译：支持模块化全操作结的结构超高压（UHV）发光二极管（LED）装置
公开(公告)号：US20120306390A1
公开(公告)日：2012-12-06
申请号：US13153011
申请日：2011-06-03
申请人： Chang-Je Li , Yi-Tsuo Wu , Yen-Liang Lin , Whu-Ming Young
发明人： Chang-Je Li , Yi-Tsuo Wu , Yen-Liang Lin , Whu-Ming Young
IPC分类号： H05B37/02
CPC分类号： H05B33/0845 , H01L25/0753 , H01L25/167 , H01L2924/0002 , H05B33/0824 , H01L2924/00
摘要： The present disclosure provides an ultra high voltage (UHV) light emitting diode (LED) device. According to one embodiment, the device includes a substrate, a plurality of LED junctions disposed above the substrate and coupled to one another, and a control component including a plurality of switches embedded within the substrate and coupled to the plurality of LED junctions to control routing of current across the plurality of LED junctions.
摘要翻译：本公开提供了一种超高压（UHV）发光二极管（LED）装置。根据一个实施例，该器件包括衬底，设置在衬底上并彼此耦合的多个LED结，以及包括嵌入在衬底内并耦合到多个LED结以控制布线的多个开关的控制部件的电流跨越多个LED结。

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